-
EP0236052
European procedure
- EP About this file
- EP Legal status
- EP Federated register
- EP Event history
- EP Citations
- EP Patent family
- EP All documents
Extract from the Register of European Patents
EP About this file: EP0236052
| EP0236052 - Memory system employing a low DC power gate array for error correction [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 16.01.1990 Database last updated on 31.08.2024 | Most recent event Tooltip | 07.07.2007 | Change - inventor | published on 08.08.2007 [2007/32] | Applicant(s) | For all designated states UNISYS CORPORATION 1, Burroughs Place Detroit Michigan 48232 / US | [N/P] |
| Former [1987/37] | For all designated states UNISYS CORPORATION 1, Burroughs Place Detroit Michigan 48232 / US | Inventor(s) | 01 /
Peterson, LuVerne Ray 16196 Rimstone Lane San Diego, CA 92127 / US | [1987/37] | Representative(s) | Kirby, Harold Douglas Benson, et al G.F. Redfern & Company Marlborough Lodge 14 Farncombe Road Worthing West Sussex BN11 2BT / GB | [N/P] |
| Former [1987/37] | Kirby, Harold Douglas Benson, et al G.F. Redfern & Company Marlborough Lodge 14 Farncombe Road Worthing West Sussex BN11 2BT / GB | Application number, filing date | 87301602.6 | 24.02.1987 | [1987/37] | Priority number, date | US19860835777 | 03.03.1986 Original published format: US 835777 | [1987/37] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0236052 | Date: | 09.09.1987 | Language: | EN | [1987/37] | Type: | A3 Search report | No.: | EP0236052 | Date: | 29.03.1989 | Language: | EN | [1989/13] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.02.1989 | Classification | IPC: | G06F11/10 | [1987/37] | CPC: |
G06F11/1008 (EP,US);
G06F11/1076 (EP,US)
| Designated contracting states | AT, BE, CH, DE, FR, GB, IT, LI, LU, NL, SE [1987/37] | Title | German: | Speichersystem unter Benutzung eines Gatterfeldes niedriger Gleichstromleistung zur Fehlerkorrektur | [1987/37] | English: | Memory system employing a low DC power gate array for error correction | [1987/37] | French: | Système de mémoire utilisant pour la correction d'erreur un réseau de portes à faible valeur d'alimentation en courant continu | [1987/37] | File destroyed: | 30.10.1997 | Examination procedure | 02.03.1987 | Examination requested [1987/37] | 30.09.1989 | Application deemed to be withdrawn, date of legal effect [1990/10] | 24.10.1989 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1990/10] | Fees paid | Renewal fee | 23.01.1989 | Renewal fee patent year 03 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]FR2292383 (SIEMENS AG [DE]); | [X]EP0081317 (TOKYO SHIBAURA ELECTRIC CO [JP]); | [A]FR2522183 (HITACHI LTD [JP]); | [A]EP0100825 (IBM [US]); | [X]JPS59125125 | [X] - PATENT ABSTRACTS OF JAPAN, vol. 8, no. 247 (E-278)[1684]13th November 1984; & JP-A-59 125 125 (FUJITSU K.K.) 19-07-1984 |