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EP0257736
European procedure
Extract from the Register of European Patents
EP About this file: EP0257736
| EP0257736 - An amplifier having a cascade circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 20.06.1997 Database last updated on 19.10.2024 | Most recent event Tooltip | 20.06.1997 | No opposition filed within time limit | published on 06.08.1997 [1997/32] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1988/09] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Kobayashi, Osamu 1472-70 Takata-cho Kohoku-ku Yokohama-shi Kanagawa 223 / JP | [1988/09] | Representative(s) | Rackham, Stephen Neil, et al Gill Jennings & Every LLP Broadgate House 7 Eldon Street London EC2M 7LH / GB | [N/P] |
| Former [1988/09] | Rackham, Stephen Neil, et al GILL JENNINGS & EVERY, Broadgate House, 7 Eldon Street London EC2M 7LH / GB | Application number, filing date | 87305036.3 | 08.06.1987 | [1988/09] | Priority number, date | JP19860134473 | 10.06.1986 Original published format: JP 13447386 | [1988/09] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0257736 | Date: | 02.03.1988 | Language: | EN | [1988/09] | Type: | B1 Patent specification | No.: | EP0257736 | Date: | 14.08.1996 | Language: | EN | [1996/33] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.11.1987 | Classification | IPC: | H03F1/22, H03F3/345 | [1988/09] | CPC: |
H03F1/086 (EP,US);
H03F1/22 (KR);
H03F1/223 (EP,US);
H03F3/45076 (EP,US)
| Designated contracting states | DE, FR, GB [1988/09] | Title | German: | Verstärker in Kaskodeschaltung | [1988/09] | English: | An amplifier having a cascade circuit | [1988/09] | French: | Amplificateur à circuit cascode | [1988/09] | Examination procedure | 09.06.1988 | Examination requested [1988/32] | 13.07.1990 | Despatch of a communication from the examining division (Time limit: M06) | 16.01.1991 | Reply to a communication from the examining division | 28.05.1993 | Despatch of a communication from the examining division (Time limit: M06) | 02.12.1993 | Reply to a communication from the examining division | 15.09.1995 | Despatch of communication of intention to grant (Approval: Yes) | 10.01.1996 | Communication of intention to grant the patent | 22.03.1996 | Fee for grant paid | 22.03.1996 | Fee for publishing/printing paid | Opposition(s) | 15.05.1997 | No opposition filed within time limit [1997/32] | Fees paid | Renewal fee | 12.06.1989 | Renewal fee patent year 03 | 12.06.1990 | Renewal fee patent year 04 | 17.06.1991 | Renewal fee patent year 05 | 09.06.1992 | Renewal fee patent year 06 | 14.06.1993 | Renewal fee patent year 07 | 11.06.1994 | Renewal fee patent year 08 | 12.06.1995 | Renewal fee patent year 09 | 10.06.1996 | Renewal fee patent year 10 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | DE | 15.11.1996 | [1997/17] | Documents cited: | Search | [AD]JP59043613 ; | [A]US3449682 (MIWA ICHIRO, et al); | [A]US4137506 (IWAMATSU MASAYUKI, et al); | [A]US4284959 (HEAGERTY WILLIAM F, et al); | [Y]GB2132435 (WESTERN ELECTRIC CO) | [Y] - IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-19, no. 6, December 1984, pages 919-925; D.B. RIBNER et al.: "Design techniques for cascoded CMOS, op amps with improved PSRR and common-mode input range" | [AD] - PATENT ABSTRACTS OF JAPAN, vol. 8, no. 131 (E-251)[1568], 19th June 1984; & JP - A - 59 043 613 (HITACHI SEISAKUSHO, TOSHIRON SUZUKI) 10-03-1984, & JP59043613 A 00000000 | [A] - ELECTRONIQUE APPLICATIONS, no. 31, August-September 1983, pages 35-44, Evry, FR; K. RISCHMÜLLER "Darlington, Bipmos, Cascode : caractéristiques et critères d'emploi" |