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EP0304035
European procedure
Extract from the Register of European Patents
EP About this file: EP0304035
| EP0304035 - Bi-mos circuit capable of high speed operation with low power consumption [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 11.12.1993 Database last updated on 24.04.2024 | Most recent event Tooltip | 11.12.1993 | No opposition filed within time limit | published on 02.02.1994 [1994/05] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [1989/08] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Yamazaki, Toru c/o NEC Corporation 33-1, Shiba 5-chome Minato-ku Tokyo / JP | [1989/08] | Representative(s) | Glawe, Delfs, Moll Partnerschaft mbB von Patent- und Rechtsanwälten Postfach 26 01 62 80058 München / DE | [N/P] |
| Former [1989/08] | Glawe, Delfs, Moll & Partner Patentanwälte Postfach 26 01 62 D-80058 München / DE | Application number, filing date | 88113356.5 | 17.08.1988 | [1989/08] | Priority number, date | JP19870203156 | 17.08.1987 Original published format: JP 20315687 | JP19880020278 | 29.01.1988 Original published format: JP 2027888 | [1989/08] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0304035 | Date: | 22.02.1989 | Language: | EN | [1989/08] | Type: | A3 Search report | No.: | EP0304035 | Date: | 12.07.1989 | Language: | EN | [1989/28] | Type: | B1 Patent specification | No.: | EP0304035 | Date: | 10.02.1993 | Language: | EN | [1993/06] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.05.1989 | Classification | IPC: | H03K19/094 | [1989/08] | CPC: |
H03K19/0013 (EP,US);
H03K19/09448 (EP,US)
| Designated contracting states | DE, FR, GB [1989/08] | Title | German: | Bimosschaltung, fähig zum Betrieb bei hoher Geschwindigkeit mit niedrigem Verbrauch | [1989/08] | English: | Bi-mos circuit capable of high speed operation with low power consumption | [1989/08] | French: | Circuit Bimos capable d'une grande vitesse de fonctionnement avec une faible consommation | [1989/08] | Examination procedure | 17.08.1988 | Examination requested [1989/08] | 06.12.1990 | Despatch of a communication from the examining division (Time limit: M06) | 07.06.1991 | Reply to a communication from the examining division | 27.03.1992 | Despatch of communication of intention to grant (Approval: Yes) | 07.08.1992 | Communication of intention to grant the patent | 22.09.1992 | Fee for grant paid | 22.09.1992 | Fee for publishing/printing paid | Opposition(s) | 11.11.1993 | No opposition filed within time limit [1994/05] | Fees paid | Renewal fee | 21.08.1990 | Renewal fee patent year 03 | 16.08.1991 | Renewal fee patent year 04 | 20.08.1992 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0209805 (HITACHI LTD [JP]); | [Y]EP0132822 (HITACHI LTD [JP]); | [X]US4675557 (HUNTINGTON ROBERT C [US]) | [YD] - NEC RESEARCH AND DEVELOPMENT, no. 84, January 1987, pages 125-130, Tokyo, JP; H. NAKASHIBA et al.: "Low power and high-speed BiCMOS gate arrays" | [AD] - VLSI DESIGN, August 1984, pages 98-100; S.-C. LEE et al.: "Bi-CMOS technology for high-performance VLSI circuits" |