-
EP0282384
European procedure
Extract from the Register of European Patents
EP About this file: EP0282384
| EP0282384 - Method and arrangement for addressing redundant elements in an integrated memory [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 06.05.1993 Database last updated on 21.05.2024 | Most recent event Tooltip | 06.05.1993 | No opposition filed within time limit | published on 23.06.1993 [1993/25] | Applicant(s) | For all designated states STMicroelectronics S.A. 7, Avenue Galliéni 94250 Gentilly / FR | [N/P] |
| Former [1991/16] | For all designated states SGS-THOMSON MICROELECTRONICS S.A. 7, Avenue Galliéni F-94250 Gentilly / FR | ||
| Former [1988/37] | For all designated states THOMSON SEMICONDUCTEURS 101, bld Murat F-75016 - Paris / FR | Inventor(s) | 01 /
Gaultier, Jean-Marie Bernard 4 bis, rue de Puyloubier F-13790 Rousset sur Arc / FR | 02 /
Devin, Jean Résidence le Ponant Allée des Cigales F-13100 Aix en Provence / FR | [1988/37] | Representative(s) | Ballot, Paul Denis Jacques, et al Cabinet Ballot 122, rue Edouard Vaillant 92593 Levallois-Perret Cedex / FR | [N/P] |
| Former [1992/14] | Ballot, Paul Denis Jacques, et al Cabinet Ballot-Schmit, 7, rue Le Sueur F-75116 Paris / FR | ||
| Former [1988/37] | Ballot, Paul Denis Jacques Cabinet Ballot-Schmit 7, rue le Sueur F-75116 Paris / FR | Application number, filing date | 88400388.0 | 19.02.1988 | [1988/37] | Priority number, date | FR19870002835 | 03.03.1987 Original published format: FR 8702835 | [1988/37] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP0282384 | Date: | 14.09.1988 | Language: | FR | [1988/37] | Type: | B1 Patent specification | No.: | EP0282384 | Date: | 01.07.1992 | Language: | FR | [1992/27] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 25.07.1988 | Classification | IPC: | G06F11/20 | [1988/37] | CPC: |
G11C29/785 (EP,US);
G11C29/808 (EP,US)
| Designated contracting states | DE, FR, GB, IT, NL [1988/37] | Title | German: | Verfahren und Anordnung zur Adressierung von redundanten Elementen eines integrierten Speichers | [1988/37] | English: | Method and arrangement for addressing redundant elements in an integrated memory | [1988/37] | French: | Procédé d'adressage d'éléments redondants d'une mémoire intégrée et dispositif permettant de mettre en oeuvre le procédé | [1988/37] | Examination procedure | 17.02.1989 | Examination requested [1989/17] | 23.10.1990 | Despatch of a communication from the examining division (Time limit: M04) | 27.12.1990 | Reply to a communication from the examining division | 17.05.1991 | Despatch of a communication from the examining division (Time limit: M02) | 03.07.1991 | Reply to a communication from the examining division | 04.11.1991 | Despatch of communication of intention to grant (Approval: Yes) | 27.12.1991 | Communication of intention to grant the patent | 20.02.1992 | Fee for grant paid | 20.02.1992 | Fee for publishing/printing paid | Opposition(s) | 02.04.1993 | No opposition filed within time limit [1993/25] | Fees paid | Renewal fee | 15.01.1990 | Renewal fee patent year 03 | 17.12.1990 | Renewal fee patent year 04 | 10.02.1992 | Renewal fee patent year 05 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | NL | 01.07.1992 | [1993/14] | Documents cited: | Search | [A]JP59048898 ; | [A]WO8001732 (WESTERN ELECTRIC CO [US]) | [A] - PATENT ABSTRACTS OF JAPAN, vol. 8, no. 151 (P-286)[1588], 13 juillet 1984; & JP-A-59 048 898 (HITACHI SEISAKUSHO K.K.) 21-03-1984, & JP59048898 A 00000000 | [A] - PROCEEDINGS OF THE IEEE, vol. 74, no. 5, mai 1986, pages 684-698, IEEE, New York, US; W.R. MOORE: "A review of fault-tolerant techniques for the enhancement of integrated circuit yield" |