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EP0335149
European procedure
Extract from the Register of European Patents
EP About this file: EP0335149
| EP0335149 - Semiconductor memory redundancy scheme [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 21.06.1996 Database last updated on 12.08.2024 | Most recent event Tooltip | 07.03.1997 | Lapse of the patent in a contracting state | published on 23.04.1997 [1997/17] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1989/40] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Fifield, John Atkinson Box 158, Packard Road Jericho Vermont 05465 / US | 02 /
Kalter, Howard Leo 14 Village Drive Colchester Vermont 05446 / US | 03 /
Miller, Christopher Paul 486D Plans Road Jericho Vermont 05465 / US | 04 /
Tomashot, Steven William RD No. 1, Box 184B Browns Trace Road Jericho Vermont 05465 / US | [1989/40] | Representative(s) | Schäfer, Wolfgang IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht 70548 Stuttgart / DE | [N/P] |
| Former [1994/37] | Schäfer, Wolfgang, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH Patentwesen und Urheberrecht D-70548 Stuttgart / DE | ||
| Former [1989/40] | Mönig, Anton, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | Application number, filing date | 89104168.3 | 09.03.1989 | [1989/40] | Priority number, date | US19880175883 | 01.04.1988 Original published format: US 175883 | [1989/40] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0335149 | Date: | 04.10.1989 | Language: | EN | [1989/40] | Type: | A3 Search report | No.: | EP0335149 | Date: | 20.03.1991 | Language: | EN | [1991/12] | Type: | B1 Patent specification | No.: | EP0335149 | Date: | 16.08.1995 | Language: | EN | [1995/33] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 29.01.1991 | Classification | IPC: | G06F11/20 | [1989/40] | CPC: |
G11C29/84 (EP,US)
| Designated contracting states | DE, FR, GB [1989/40] | Title | German: | Halbleiterspeicherredundanzsystem | [1989/40] | English: | Semiconductor memory redundancy scheme | [1989/40] | French: | Agencement de redondance de mémoire à semi-conducteur | [1989/40] | Examination procedure | 24.02.1990 | Examination requested [1990/17] | 11.03.1994 | Despatch of a communication from the examining division (Time limit: M04) | 18.07.1994 | Reply to a communication from the examining division | 13.10.1994 | Despatch of communication of intention to grant (Approval: Yes) | 16.02.1995 | Communication of intention to grant the patent | 01.03.1995 | Fee for grant paid | 01.03.1995 | Fee for publishing/printing paid | Opposition(s) | 18.05.1996 | No opposition filed within time limit [1996/32] | Fees paid | Renewal fee | 13.12.1990 | Renewal fee patent year 03 | 16.03.1992 | Renewal fee patent year 04 | 31.03.1993 | Renewal fee patent year 05 | 24.03.1994 | Renewal fee patent year 06 | 23.03.1995 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | GB | 09.03.1996 | [1997/17] | Documents cited: | Search | [AD]US4389715 (EATON JR SARGENT S, et al); | [A]EP0146357 (FUJITSU LTD [JP]) | [XD] - IBM J. RES. DEVELOP., vol. 24, no. 3, May 1980, pages 291-298, New York, US; B.F. FITZGERALD et al.: "Circuit implementation of fusible redundant addresses on RAMs for productivity enhancement" | [A] - 1979 IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, 1979, pages 150,151,290,291, IEEE, New York, US; R.P. CENKER et al.: "A fault-tolerant 64K dynamic RAM" |