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Extract from the Register of European Patents

EP About this file: EP0334240

EP0334240 - Semiconductor integrated circuit device having a microprogramm [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  22.11.1996
Database last updated on 13.07.2024
Most recent event   Tooltip22.11.1996No opposition filed within time limitpublished on 08.01.1997 [1997/02]
Applicant(s)For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku Kawasaki-shi
Kanagawa 211 / JP
[N/P]
Former [1989/39]For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku
Kawasaki-shi, Kanagawa 211 / JP
Inventor(s)01 / Taniai, Takayoshi
1339, Shimosakunobe Takatsu-ku
Kawasaki-shi Kanagawa, 213 / JP
02 / Nagasawa, Tatsuya
1-1-2, Kanumadai
Sagamihara-shi Kanagawa, 229 / JP
[1989/39]
Representative(s)Seeger, Wolfgang
Seeger & Seeger
Patentanwälte & European Patent Attorneys
Georg-Hager-Strasse 40
81369 München / DE
[N/P]
Former [1989/39]Seeger, Wolfgang, Dipl.-Phys.
SEEGER & SEEGER Patentanwälte & European Patent Attorneys Georg-Hager-Strasse 40
D-81369 München / DE
Application number, filing date89104851.417.03.1989
[1989/39]
Priority number, dateJP1988007142625.03.1988         Original published format: JP 7142688
[1989/39]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0334240
Date:27.09.1989
Language:EN
[1989/39]
Type: A3 Search report 
No.:EP0334240
Date:17.04.1991
Language:EN
[1991/16]
Type: B1 Patent specification 
No.:EP0334240
Date:17.01.1996
Language:EN
[1996/03]
Search report(s)(Supplementary) European search report - dispatched on:EP27.02.1991
ClassificationIPC:G06F9/26
[1996/03]
CPC:
G06F9/268 (EP,US); G06F11/28 (KR); G06F9/26 (EP,US);
H01L27/02 (KR)
Former IPC [1989/39]G06F9/22
Designated contracting statesFR [1995/36]
Former [1989/39]DE,  FR,  GB 
TitleGerman:Integrierte Halbleiterschaltungsanordnung mit Mikroprogramm[1989/39]
English:Semiconductor integrated circuit device having a microprogramm[1989/39]
French:Dispositif de circuit intégré à semi-conducteur avec microprogramme[1989/39]
Examination procedure24.06.1991Examination requested  [1991/35]
21.06.1994Despatch of a communication from the examining division (Time limit: M04)
17.10.1994Reply to a communication from the examining division
18.05.1995Despatch of communication of intention to grant (Approval: Yes)
24.07.1995Communication of intention to grant the patent
05.09.1995Fee for grant paid
05.09.1995Fee for publishing/printing paid
Opposition(s)18.10.1996No opposition filed within time limit [1997/02]
Fees paidRenewal fee
22.03.1991Renewal fee patent year 03
26.03.1992Renewal fee patent year 04
23.03.1993Renewal fee patent year 05
28.03.1994Renewal fee patent year 06
24.03.1995Renewal fee patent year 07
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Documents cited:Search[A]US4275441  (TAKEUCHI HIROSHI);
 [A]US4677586  (MAGAR SURENDAR S [US], et al)
 [A]  - 18TH ANNUAL WORKSHOP ON MICROPROGRAMMING, Pacific Grove, CA, 3rd - 6th December 1985, pages 35-46, IEEE, New York, US; F.J. BURKOWSKI: "An interactive diagnostic/debugging subsystem for bit-slice processors"
 [A]  - E.D.N. ELECTRICAL DESIGN NEWS, vol. 32, no. 7, 31st March 1987, pages 191-196, Newton, MA, US; B. RICHARDSON: "Microprogram monitor helps develop bit-slice designs"
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.