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EP0363465
European procedure
Extract from the Register of European Patents
EP About this file: EP0363465
| EP0363465 - TEST PROGRAMME GENERATION ASSISTING APPARATUS FOR DIGITAL CIRCUITS [Right-click to bookmark this link] | |||
| Former [1990/16] | TEST PROGRAMME GENERATION ASSISTING MEANS FOR DIGITAL CIRCUITS | ||
| [1993/44] | Status | No opposition filed within time limit Status updated on 03.09.1994 Database last updated on 05.10.2024 | Most recent event Tooltip | 15.08.2008 | Change - applicant | published on 17.09.2008 [2008/38] | Applicant(s) | For all designated states Hewlett-Packard Company 3000 Hanover Street Palo Alto, CA 94304-1112 / US | [N/P] |
| Former [2008/38] | For all designated states Hewlett-Packard Company 3000 Hanover Street Palo Alto CA 94304-1112 / US | ||
| Former [1991/02] | For all designated states Hewlett-Packard Company Mail Stop 20 B-O, 3000 Hanover Street Palo Alto, California 94304 / US | ||
| Former [1990/16] | For all designated states Hewlett-Packard Company 3000 Hanover Street Palo Alto California 94304 / US | Inventor(s) | 01 /
WELHAM, Robert, Kenneth Hewlett-Packard Limited Filton Road Stoke Gifford Bristol 12 6QZ / GB | 02 /
GUPTA, Ajay Hewlett-Packard India Swindsor Place - 6th Floor Janpath, New Delhi 16001 / IN | [1990/16] | Representative(s) | Kilgannon, Denise Mary Hewlett-Packard Limited, Building 2, Intellectual Property Section, Filton Road Stoke Gifford, Bristol BS12 6QZ / GB | [N/P] |
| Former [1992/40] | Smith, Denise Mary Hewlett-Packard Limited, Building 2, Intellectual Property Section, Filton Road Stoke Gifford, Bristol BS12 6QZ / GB | ||
| Former [1990/16] | Smith, Denise Mary Hewlett-Packard Limited Cain Road Bracknell, Berkshire RG12 1HN / GB | Application number, filing date | 89904134.7 | 03.03.1989 | [1990/16] | WO1989GB00209 | Priority number, date | GB19880005120 | 03.03.1988 Original published format: GB 8805120 | [1990/16] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO8908297 | Date: | 08.09.1989 | Language: | EN | [1989/21] | Type: | A1 Application with search report | No.: | EP0363465 | Date: | 18.04.1990 | Language: | EN | The application published by WIPO in one of the EPO official languages on 08.09.1989 takes the place of the publication of the European patent application. | [1990/16] | Type: | B1 Patent specification | No.: | EP0363465 | Date: | 03.11.1993 | Language: | EN | [1993/44] | Search report(s) | International search report - published on: | EP | 08.09.1989 | Classification | IPC: | G06F11/26 | [1990/16] | CPC: |
G01R31/318307 (EP,US)
| Designated contracting states | DE, FR, GB [1990/16] | Title | German: | GERäT ZUR RECHNERGESTÜTZEN ERZEUGUNG VON PRÜFPROGRAMMEN FÜR DIGITALE SCHALTUNGEN | [1993/44] | English: | TEST PROGRAMME GENERATION ASSISTING APPARATUS FOR DIGITAL CIRCUITS | [1993/44] | French: | DISPOSITIF D'ASSISTANCE DE GENERATION DE TEST POUR CIRCUITS DIGITAUX | [1993/44] |
| Former [1990/16] | RECHNERGESTÜTZE ERZEUGUNG VON PRÜFPROGRAMMEN FÜR DIGITALE SCHALTUNGEN | ||
| Former [1990/16] | TEST PROGRAMME GENERATION ASSISTING MEANS FOR DIGITAL CIRCUITS | ||
| Former [1990/16] | PROCEDE AUXILIAIRE DE GENERATION DE PROGRAMMES D'ESSAI POUR CIRCUITS NUMERIQUES | Entry into regional phase | 21.10.1989 | National basic fee paid | 21.10.1989 | Designation fee(s) paid | 21.10.1989 | Examination fee paid | Examination procedure | 21.10.1989 | Examination requested [1990/16] | 02.03.1992 | Despatch of a communication from the examining division (Time limit: M06) | 26.08.1992 | Reply to a communication from the examining division | 08.01.1993 | Despatch of communication of intention to grant (Approval: No) | 30.04.1993 | Despatch of communication of intention to grant (Approval: later approval) | 07.05.1993 | Communication of intention to grant the patent | 21.05.1993 | Fee for grant paid | 21.05.1993 | Fee for publishing/printing paid | Opposition(s) | 04.08.1994 | No opposition filed within time limit [1994/43] | Fees paid | Renewal fee | 17.12.1990 | Renewal fee patent year 03 | 09.01.1992 | Renewal fee patent year 04 | 12.03.1993 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Cited in | International search | [A] - 7th European Conference on Electrotechnics, Advanced Technologies and Processes in Communication and Power Systems, 21-23 April 1986, Paris, Session A. II: New Software and Expert Systems, Communication AII-1, R. Lbath et al.: "A test pattern generation environment for complex test digital circuits" pages 66-72 | [A] - IEEE Design & Test of Computer, volume 2, no. 5, October 1985, IEEE; (New York, US), Shigehiro Funatsu et al.: "An automatic test-generation system for large digital circuits", pages 54-60 | [A] - Electronics, volume 54, no. 24, 30 November 1981, (New York, US), R. Hickling et al.: "Automating test generation closes the design loop", pages 129-133 | [A] - Proceedings National Conference on Artifical Intelligence, 1982, M.R. Genesereth: "Diagnosis using hierarchical design models"; pages 278-283 |