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Extract from the Register of European Patents

EP About this file: EP0402966

EP0402966 - Method for treating copper circuit pattern of interlayer circuit board [Right-click to bookmark this link]
StatusThe application is deemed to be withdrawn
Status updated on  07.12.1993
Database last updated on 30.10.2024
Most recent event   Tooltip07.12.1993Application deemed to be withdrawnpublished on 26.01.1994 [1994/04]
Applicant(s)For all designated states
MATSUSHITA ELECTRIC WORKS, LTD.
1048, Oaza-Kadoma
Kadoma-shi, Osaka 571 / JP
[N/P]
Former [1990/51]For all designated states
MATSUSHITA ELECTRIC WORKS, LTD.
1048, Oaza-Kadoma
Kadoma-shi Osaka 571 / JP
Inventor(s)01 / Awano, Tomio, c/o Matsushita Electric Works, Ltd.
1048, Oaza-Kadoma, Kadoma-shi
Osaka 571 / JP
02 / Akamatsu, Motoyuki, c/o Matsushita Electric Works
Ltd., 1048, Oaza-Kadoma, Kadoma-shi
Osaka 571 / JP
03 / Yamane, Tomoaki, c/o Matsushita Electric Works
Ltd., 1048, Oaza-Kadoma, Kadoma-shi
Osaka 571 / JP
04 / Ichiki, Tsutomu, c/o Matsushita Electric Works
Ltd., 1048, Oaza-Kadoma, Kadoma-shi
Osaka 571 / JP
05 / Funo, Hideo, c/o Matsushita Electric Works
Ltd., 1048, Oaza-Kadoma, Kadoma-shi
Osaka 571 / JP
06 / Sagara, Takashi, c/o Matsushita Electric Works
Ltd., 1048, Oaza-Kadoma, Kadoma-shi
Osaka 571 / JP
[1990/51]
Representative(s)Kupecz, Arpad, et al
Octrooibureau Los en Stigter B.V.
P.O. Box 20052
1000 HB Amsterdam / NL
[N/P]
Former [1990/51]Kupecz, Arpad, et al
Octrooibureau Los en Stigter B.V. Postbox 20052
NL-1000 HB Amsterdam / NL
Application number, filing date90201118.803.05.1990
[1990/51]
Priority number, dateJP1989015270215.06.1989         Original published format: JP 15270289
[1990/51]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0402966
Date:19.12.1990
Language:EN
[1990/51]
Type: A3 Search report 
No.:EP0402966
Date:10.04.1991
Language:EN
[1991/15]
Search report(s)(Supplementary) European search report - dispatched on:EP22.02.1991
ClassificationIPC:H05K3/46, H05K3/38
[1990/51]
CPC:
H05K3/385 (EP); H05K3/46 (KR); H05K2203/0315 (EP);
H05K2203/1157 (EP); H05K3/4611 (EP)
Designated contracting statesDE,   GB,   IT [1990/51]
TitleGerman:Verfahren zur Behandlung eines Kupferschaltungsmusters einer inneren Leiterplatte[1990/51]
English:Method for treating copper circuit pattern of interlayer circuit board[1990/51]
French:Procédé de traitement du circuit en cuivre d'une plaquette de circuit interne[1990/51]
File destroyed:12.06.1999
Examination procedure30.11.1990Examination requested  [1991/04]
17.03.1993Despatch of a communication from the examining division (Time limit: M04)
28.07.1993Application deemed to be withdrawn, date of legal effect  [1994/04]
26.08.1993Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time  [1994/04]
Fees paidRenewal fee
01.06.1992Renewal fee patent year 03
01.06.1993Renewal fee patent year 04
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Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Documents cited:Search[A]US4795512  (NAKATANI SEIICHI [JP], et al);
 [AD]EP0189913  (HITACHI LTD [JP]);
 [A]US4328048  (SENDA ATSUO, et al);
 [AP]EP0321067  (HITACHI CHEMICAL CO LTD [JP])
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.