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EP0399762
European procedure
Extract from the Register of European Patents
EP About this file: EP0399762
| EP0399762 - Multiple instruction issue computer architecture [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 21.10.2000 Database last updated on 30.10.2024 | Most recent event Tooltip | 18.05.2001 | Lapse of the patent in a contracting state | published on 04.07.2001 [2001/27] | Applicant(s) | For all designated states TANDEM COMPUTERS INCORPORATED 10435 North Tantau Avenue Cupertino, California 95014 / US | [1999/17] |
| Former [1990/48] | For all designated states TANDEM COMPUTERS INCORPORATED 19333 Vallco Parkway Cupertino California 95014-2599 / US | Inventor(s) | 01 /
Horst, Robert W. 2804 Robeson Park Drive Champaign, Illinois 61821 / US | [1992/19] |
| Former [1990/48] | 01 /
Horse, Robert W. 2804 Robeson Park Drive Champaign, Illinois 61821 / US | Representative(s) | Ayers, Martyn Lewis Stanley, et al J A Kemp 14 South Square Gray's Inn London WC1R 5JJ / GB | [N/P] |
| Former [1994/28] | Ayers, Martyn Lewis Stanley, et al J.A. KEMP & CO. 14 South Square Gray's Inn London WC1R 5LX / GB | ||
| Former [1990/48] | Ayers, Martyn Lewis Stanley J.A. KEMP & CO. 14 South Square Gray's Inn London WC1R 5LX / GB | Application number, filing date | 90305489.8 | 21.05.1990 | [1990/48] | Priority number, date | US19890356170 | 24.05.1989 Original published format: US 356170 | [1990/48] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0399762 | Date: | 28.11.1990 | Language: | EN | [1990/48] | Type: | A3 Search report | No.: | EP0399762 | Date: | 22.01.1992 | Language: | EN | [1992/04] | Type: | B1 Patent specification | No.: | EP0399762 | Date: | 22.12.1999 | Language: | EN | [1999/51] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.12.1991 | Classification | IPC: | G06F9/38 | [1990/48] | CPC: |
G06F9/30134 (EP,US);
G06F9/261 (EP,US);
G06F9/3802 (EP,US);
G06F9/3838 (EP,US);
G06F9/3844 (EP,US);
G06F9/3853 (EP,US);
G06F9/3861 (EP,US)
(-)
| Designated contracting states | DE, FR, GB, IT, SE [1990/48] | Title | German: | Rechnerarchitektur mit Mehrfachbefehlsausgabe | [1990/48] | English: | Multiple instruction issue computer architecture | [1990/48] | French: | Architecture de calculateur à délivrance multiple des instructions | [1990/48] | Examination procedure | 10.07.1992 | Examination requested [1992/37] | 08.07.1996 | Despatch of a communication from the examining division (Time limit: M06) | 14.01.1997 | Reply to a communication from the examining division | 26.02.1998 | Despatch of a communication from the examining division (Time limit: M06) | 31.08.1998 | Reply to a communication from the examining division | 25.01.1999 | Despatch of communication of intention to grant (Approval: Yes) | 14.06.1999 | Communication of intention to grant the patent | 08.09.1999 | Fee for grant paid | 08.09.1999 | Fee for publishing/printing paid | Divisional application(s) | EP98122872.9 / EP0902362 | Opposition(s) | 23.09.2000 | No opposition filed within time limit [2000/49] | Fees paid | Renewal fee | 24.03.1992 | Renewal fee patent year 03 | 18.03.1993 | Renewal fee patent year 04 | 29.03.1994 | Renewal fee patent year 05 | 29.03.1995 | Renewal fee patent year 06 | 03.04.1996 | Renewal fee patent year 07 | 26.03.1997 | Renewal fee patent year 08 | 25.03.1998 | Renewal fee patent year 09 | 29.03.1999 | Renewal fee patent year 10 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | SE | 22.05.2000 | [2001/27] | Documents cited: | Search | [Y]EP0071028 (IBM [US]); | [X]EP0118830 (IBM [US]); | [A]EP0155211 (FUJITSU LTD [JP]); | [X]EP0239081 (HITACHI LTD [JP]); | [XP]EP0354740 (MATSUSHITA ELECTRIC IND CO LTD [JP]) | [XP] - HIGH PERFORMANCE SYSTEMS vol. 10, no. 12, December 1989, CMP PUBLICATION, MANHASSET, NEW YORK pages 53 - 60; S. CHAN, R. HORST: 'Bulding Parallelism into the Instruction Pipeline' | [Y] - IBM TECHNICAL DISCLOSURE BULLETIN. vol. 29, no. 2, July 1986, NEW YORK US pages 605 - 608; 'Data Bypass Methodology for a Performance Pipeline Processor' | [A] - * the whole document * |