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EP0426282
European procedure
Extract from the Register of European Patents
EP About this file: EP0426282
| EP0426282 - Programmable logic device [Right-click to bookmark this link] | |||
| Former [1991/19] | Three transistor EEPROM cell | ||
| [1997/44] | Status | No opposition filed within time limit Status updated on 04.09.1998 Database last updated on 13.07.2024 | Most recent event Tooltip | 04.09.1998 | No opposition filed within time limit | published on 21.10.1998 [1998/43] | Applicant(s) | For all designated states STMicroelectronics, Inc. 1310 Electronics Drive Carrollton, TX 75006-5039 / US | [N/P] |
| Former [1991/19] | For all designated states SGS-THOMSON MICROELECTRONICS, INC. 1310 Electronics Drive Carrollton Texas 75006 / US | Inventor(s) | 01 /
Doyle, Bruce Andrew 5317 Valleydale Drive Flower Mound, Texas 75028 / US | 02 /
Steele, Randy Charles 1335 Woodbrook Lane Southlake, Texas 76092 / US | 03 /
Raad, Safoin Assaf 7356 Parkridge Blvd. No 388 Irving, Texas 75063 / US | [1991/19] | Representative(s) | Palmer, Roger, et al PAGE, WHITE & FARRER 54 Doughty Street London WC1N 2LS / GB | [1991/19] | Application number, filing date | 90309521.4 | 30.08.1990 | [1991/19] | Priority number, date | US19890429308 | 31.10.1989 Original published format: US 429308 | [1991/19] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0426282 | Date: | 08.05.1991 | Language: | EN | [1991/19] | Type: | A3 Search report | No.: | EP0426282 | Date: | 13.05.1992 | Language: | EN | [1992/20] | Type: | B1 Patent specification | No.: | EP0426282 | Date: | 29.10.1997 | Language: | EN | [1997/44] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.03.1992 | Classification | IPC: | G11C16/04 | [1991/19] | CPC: |
G11C16/0433 (EP,US);
G11C16/00 (KR);
H10B69/00 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1991/19] | Title | German: | Programmierbare logische Vorrichtung | [1997/44] | English: | Programmable logic device | [1997/44] | French: | Dispositif logique programmable | [1997/44] |
| Former [1991/19] | EEPROM-Zelle mit drei Transistoren | ||
| Former [1991/19] | Three transistor EEPROM cell | ||
| Former [1991/19] | Cellule EEPROM à trois transistors | Examination procedure | 29.10.1992 | Examination requested [1992/53] | 16.12.1994 | Despatch of a communication from the examining division (Time limit: M06) | 23.06.1995 | Reply to a communication from the examining division | 19.01.1996 | Despatch of a communication from the examining division (Time limit: M06) | 03.07.1996 | Reply to a communication from the examining division | 10.12.1996 | Despatch of communication of intention to grant (Approval: Yes) | 10.03.1997 | Communication of intention to grant the patent | 27.05.1997 | Fee for grant paid | 27.05.1997 | Fee for publishing/printing paid | Opposition(s) | 30.07.1998 | No opposition filed within time limit [1998/43] | Fees paid | Renewal fee | 21.08.1992 | Renewal fee patent year 03 | 23.08.1993 | Renewal fee patent year 04 | 04.08.1994 | Renewal fee patent year 05 | 11.08.1995 | Renewal fee patent year 06 | 09.08.1996 | Renewal fee patent year 07 | 26.08.1997 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]WO8202275 (NCR CO [US]); | [X]EP0284724 (TOSHIBA KK [JP], et al) | [A] - IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE. vol. 33, 21 February 1986, NEW YORK US pages 240 - 241; RUTLEDGE ET AL: 'A 16ns CMOS EEPLA with Reprogrammable Architecture' | [A] - ELECTRONICS. vol. 53, no. 5, 28 February 1980, NEW YORK US pages 113 - 117; JOHNSON ET AL: '16-k EE-PROM relies on tunneling for byte-erasable program storage' |