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EP0419302
European procedure
Extract from the Register of European Patents
EP About this file: EP0419302
| EP0419302 - A method of manufacturing semiconductor on insulator [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 27.08.1994 Database last updated on 17.07.2024 | Most recent event Tooltip | 27.08.1994 | No opposition filed within time limit | published on 19.10.1994 [1994/42] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1991/13] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Fujioka, Hiroshi 15-19-901, Nishikata 1-chome Bunkyo-ku, Tokyo 113 / JP | [1991/13] | Representative(s) | Joly, Jean-Jacques, et al Cabinet Beau de Loménie 158, rue de l'Université 75340 Paris cedex 07 / FR | [N/P] |
| Former [1991/13] | Joly, Jean-Jacques, et al Cabinet Beau de Loménie 158, rue de l'Université F-75340 Paris Cédex 07 / FR | Application number, filing date | 90402260.5 | 07.08.1990 | [1991/13] | Priority number, date | JP19890213428 | 19.08.1989 Original published format: JP 21342889 | [1991/13] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0419302 | Date: | 27.03.1991 | Language: | EN | [1991/13] | Type: | B1 Patent specification | No.: | EP0419302 | Date: | 27.10.1993 | Language: | EN | [1993/43] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.02.1991 | Classification | IPC: | H01L21/76, H01L21/324 | [1991/13] | CPC: |
H01L21/26533 (EP,US);
H01L21/324 (EP,US);
H01L21/76264 (EP,US);
H01L21/76267 (EP,US);
H01L21/76283 (EP,US)
| Designated contracting states | DE, FR, GB [1991/13] | Title | German: | Verfahren zur Herstellung einer SOI-Halbleiteranordnung | [1991/13] | English: | A method of manufacturing semiconductor on insulator | [1991/13] | French: | Procédé de fabrication d'un dispositif semi-conducteur du type SOI | [1991/13] | Examination procedure | 02.09.1991 | Examination requested [1991/44] | 31.10.1991 | Despatch of a communication from the examining division (Time limit: M04) | 13.02.1992 | Reply to a communication from the examining division | 16.10.1992 | Despatch of communication of intention to grant (Approval: No) | 24.02.1993 | Despatch of communication of intention to grant (Approval: later approval) | 02.03.1993 | Communication of intention to grant the patent | 05.05.1993 | Fee for grant paid | 05.05.1993 | Fee for publishing/printing paid | Opposition(s) | 28.07.1994 | No opposition filed within time limit [1994/42] | Fees paid | Renewal fee | 19.08.1992 | Renewal fee patent year 03 | 21.08.1993 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0060676 (FUJITSU LTD [JP]); | [A]EP0269349 (AMERICAN TELEPHONE & TELEGRAPH [US]) | [A] - JOURNAL OF APPLIED PHYSICS, vol. 59, no. 10, May 1986, pages 3495-3502, American Institute of Physics, Woodbury, New York, US; H.J. STEIN et al.: "Rapid thermal annealing and regrowth of thermal donors in silicon" |