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Extract from the Register of European Patents

EP About this file: EP0473911

EP0473911 - Method for mounting electronic parts on a printed circuit board [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  19.08.1995
Database last updated on 14.09.2024
Most recent event   Tooltip07.06.1996Lapse of the patent in a contracting statepublished on 24.07.1996 [1996/30]
Applicant(s)For all designated states
TDK Corporation
13-1, Nihonbashi 1-chome Chuo-ku
Tokyo / JP
[N/P]
Former [1992/11]For all designated states
TDK CORPORATION
13-1, Nihonbashi 1-chome
Chuo-ku Tokyo / JP
Inventor(s)01 / Tamashima, Jun
c/o TDK Corporation, 13-1, Nihonbashi 1-chome
Chuo-ku, Tokyo / JP
02 / Ide, Masatoshi
c/o TDK Corporation, 13-1, Nihonbashi 1-chome
Chuo-ku, Tokyo / JP
[1992/11]
Representative(s)Schwan, Gerhard
Schwan Schwan Schorer
Patentanwälte
Bauerstrasse 22
80796 München / DE
[N/P]
Former [1992/11]Schwan, Gerhard, Dipl.-Ing.
Elfenstrasse 32
D-81739 München / DE
Application number, filing date91111796.815.07.1991
[1992/11]
Priority number, dateJP1990023442106.09.1990         Original published format: JP 23442190
[1992/11]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0473911
Date:11.03.1992
Language:EN
[1992/11]
Type: A3 Search report 
No.:EP0473911
Date:27.01.1993
Language:EN
[1993/04]
Type: B1 Patent specification 
No.:EP0473911
Date:19.10.1994
Language:EN
[1994/42]
Search report(s)(Supplementary) European search report - dispatched on:EP10.12.1992
ClassificationIPC:H05K13/04, H05K3/34, H01L21/00
[1993/04]
CPC:
H05K13/0469 (EP,US); H05K3/30 (KR); H05K3/305 (EP,US);
H05K2201/0129 (EP,US); H05K2201/0162 (EP,US); H05K2203/013 (EP,US);
H05K2203/0786 (EP,US); H05K2203/102 (EP,US); Y02P70/50 (EP,US);
Y10T156/1092 (EP,US) (-)
Former IPC [1992/11]H05K13/04
Designated contracting statesDE,   FR,   GB,   NL [1992/11]
TitleGerman:Verfahren zur Montage von elektronischen Bauteilen auf einer Leiterplatte[1992/11]
English:Method for mounting electronic parts on a printed circuit board[1992/11]
French:Méthode pour le montage de composants électroniques sur une plaquette à circuit imprimé[1992/11]
File destroyed:20.04.2002
Examination procedure14.01.1993Examination requested  [1993/11]
24.11.1993Despatch of communication of intention to grant (Approval: Yes)
13.01.1994Communication of intention to grant the patent
07.04.1994Fee for grant paid
07.04.1994Fee for publishing/printing paid
Opposition(s)20.07.1995No opposition filed within time limit [1995/41]
Fees paidRenewal fee
21.07.1993Renewal fee patent year 03
25.07.1994Renewal fee patent year 04
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competence of the Unified
Patent Court
See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipGB15.07.1995
[1996/30]
Documents cited:Search[A]EP0219177  (PHILIPS PATENTVERWALTUNG [DE], et al);
 [A]US3963551  (MARLINSKI EDWARD J);
 [A]EP0171466  (SIEMENS AG [DE]);
 [A]WO8501634  (DORTRELL LTD [GB]);
 [A]FR2109716  (IBM);
 [AD]US4314870  (ISHIDA TOSHIMICHI, et al)
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.