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EP0468480
European procedure
Extract from the Register of European Patents
EP About this file: EP0468480
| EP0468480 - Synchronous burst-access memory and word-line driving circuit therefor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 07.11.1997 Database last updated on 17.05.2024 | Most recent event Tooltip | 07.11.1997 | No opposition filed within time limit | published on 29.12.1997 [1997/52] | Applicant(s) | For all designated states Oki Electric Industry Co., Ltd. 7-12, Toranomon 1-chome Minato-ku Tokyo / JP | [N/P] |
| Former [1992/05] | For all designated states Oki Electric Industry Co., Ltd. 7-12, Toranomon 1-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Takasugi, Atsushi, c/o Oki Electric Ind. Co., Ltd. 7-12, Toranomon 1-chome Minato-ku, Tokyo / JP | [1992/05] | Representative(s) | Betten & Resch Patent- und Rechtsanwälte PartGmbB Postfach 10 02 51 80076 München / DE | [N/P] |
| Former [1992/05] | Betten & Resch Reichenbachstrasse 19 D-80469 München / DE | Application number, filing date | 91112424.6 | 24.07.1991 | [1992/05] | Priority number, date | JP19900196877 | 25.07.1990 Original published format: JP 19687790 | JP19900259697 | 28.09.1990 Original published format: JP 25969790 | [1992/05] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0468480 | Date: | 29.01.1992 | Language: | EN | [1992/05] | Type: | A3 Search report | No.: | EP0468480 | Date: | 30.12.1992 | Language: | EN | [1992/53] | Type: | B1 Patent specification | No.: | EP0468480 | Date: | 02.01.1997 | Language: | EN | [1997/01] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.11.1992 | Classification | IPC: | G11C7/00 | [1992/05] | CPC: |
G11C7/1018 (EP,US);
G11C11/40 (KR);
G11C7/1072 (EP,US);
G11C8/00 (EP,US);
G11C8/18 (EP,US)
| Designated contracting states | DE, FR, GB [1992/05] | Title | German: | Synchronisierter Burstzugriffsspeicher und Wortleitungstreiber dafür | [1992/05] | English: | Synchronous burst-access memory and word-line driving circuit therefor | [1992/05] | French: | Mémoire à accès à rafale synchronisée et circuit d'attaque de ligne de mot pour celle-ci | [1992/05] | Examination procedure | 23.04.1993 | Examination requested [1993/25] | 11.08.1995 | Despatch of a communication from the examining division (Time limit: M04) | 13.12.1995 | Reply to a communication from the examining division | 26.03.1996 | Despatch of communication of intention to grant (Approval: Yes) | 05.07.1996 | Communication of intention to grant the patent | 07.10.1996 | Fee for grant paid | 07.10.1996 | Fee for publishing/printing paid | Opposition(s) | 03.10.1997 | No opposition filed within time limit [1997/52] | Fees paid | Renewal fee | 27.07.1993 | Renewal fee patent year 03 | 28.07.1994 | Renewal fee patent year 04 | 27.07.1995 | Renewal fee patent year 05 | 29.07.1996 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0135940 (NEC CORP [JP]); | [A]US4513372 (ZIEGLER MICHAEL L [US], et al) | [A] - ELECTRONIC DESIGN. vol. 36, no. 19, 25 August 1988, HASBROUCK HEIGHTS, NEW JERSEY pages 93 - 96 SHAKAIB IQBAL 'INTERNALLY TIMED RAMs BUILD FAST WRITABLE CONTROL STORES' |