-
EP0489394
European procedure
Extract from the Register of European Patents
EP About this file: EP0489394
| EP0489394 - Semiconductor integrated circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 22.05.1998 Database last updated on 24.08.2024 | Most recent event Tooltip | 22.05.1998 | No opposition filed within time limit | published on 08.07.1998 [1998/28] | Applicant(s) | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi Osaka 571-8501 / JP | [N/P] |
| Former [1994/50] | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Ohaza Kadoma Kadoma-shi, Osaka-fu, 571 / JP | ||
| Former [1992/24] | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD 1006-banchi, Oaza-Kadoma Kadoma-shi, Osaka 571 / JP | Inventor(s) | 01 /
Imai, Kiyoshi, 803, Lionsmansion Nijojo Higashi Oikeagaru, Aburanokoji-dori Nakagyo-ku, Kyoto-shi, Kyoto / JP | 02 /
Tsuji, Toshiaki Syoji-ryo, 3-5, Togu-cho Ibaraki-shi, Osaka / JP | 03 /
Takada, Taku Suncity Kosen, 4-47, Akamatsu-cho Chigasaki-shi, Kanagawa / JP | 04 /
Taguchi, Seiichi A-105, Fushimisou, 138-8, Hazukashi Shimizu-cho, Fushimi-ku, Kyoto / JP | [1992/24] | Representative(s) | Eisenführ Speiser Patentanwälte Rechtsanwälte PartGmbB Postfach 10 60 78 28060 Bremen / DE | [N/P] |
| Former [1992/24] | Eisenführ, Speiser & Partner Martinistrasse 24 D-28195 Bremen / DE | Application number, filing date | 91120719.9 | 03.12.1991 | [1992/24] | Priority number, date | JP19900400584 | 06.12.1990 Original published format: JP 40058490 | [1992/24] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0489394 | Date: | 10.06.1992 | Language: | EN | [1992/24] | Type: | A3 Search report | No.: | EP0489394 | Date: | 23.06.1993 | Language: | EN | [1993/25] | Type: | B1 Patent specification | No.: | EP0489394 | Date: | 16.07.1997 | Language: | EN | [1997/29] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.05.1993 | Classification | IPC: | G06F11/22, G06F11/26 | [1997/29] | CPC: |
G01R31/3167 (EP,US);
H03M1/12 (KR);
G01R31/318536 (EP,US)
|
| Former IPC [1992/24] | G01R31/318 | Designated contracting states | DE, FR, GB [1992/24] | Title | German: | Integrierte Halbleiterschaltung | [1992/24] | English: | Semiconductor integrated circuit | [1992/24] | French: | Circuit intégré à semi-conducteur | [1992/24] | Examination procedure | 03.12.1991 | Examination requested [1992/24] | 04.12.1995 | Despatch of a communication from the examining division (Time limit: M04) | 10.04.1996 | Reply to a communication from the examining division | 07.06.1996 | Despatch of a communication from the examining division (Time limit: M02) | 07.08.1996 | Reply to a communication from the examining division | 29.10.1996 | Despatch of communication of intention to grant (Approval: Yes) | 20.12.1996 | Communication of intention to grant the patent | 01.04.1997 | Fee for grant paid | 01.04.1997 | Fee for publishing/printing paid | Opposition(s) | 17.04.1998 | No opposition filed within time limit [1998/28] | Fees paid | Renewal fee | 22.12.1993 | Renewal fee patent year 03 | 27.12.1994 | Renewal fee patent year 04 | 27.12.1995 | Renewal fee patent year 05 | 24.12.1996 | Renewal fee patent year 06 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]DE3305547 (PHILIPS PATENTVERWALTUNG [DE]) | [Y] - PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, May 15-18, 1989, pages 22.4.1-22.4.4, IEEE, New York, US; P.P.FASANG:'Boundary scan and its applica tion to analog-digital ASIC testing in a board/system environment' | [Y] - IEE PROCEEDINGS I. SOLID- STATE & ELECTRON DEVICES vol. 132, no. 2, March 1985, STEVENAGE GB pages 121 - 129 K.A.E. TOTTON ET AL. 'Review of built-in test methologies for gate arrays' | [A] - PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, May 4-7, 1987, pages 492-497, IEEE, New York, US; H.G. THONEMANN et al.:'VENUS - An advanced VLSI design environment for custom integrated circuits with macro cells, standard cells and gate arrays' |