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EP0465322
European procedure
Extract from the Register of European Patents
EP About this file: EP0465322
| EP0465322 - In-register data manipulation in reduced instruction set processor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 21.07.2000 Database last updated on 07.06.2024 | Most recent event Tooltip | 28.12.2002 | Lapse of the patent in a contracting state | published on 12.02.2003 [2003/07] | Applicant(s) | For all designated states DIGITAL EQUIPMENT CORPORATION 146 Main Street Maynard, MA 01754 / US | [1992/02] | Inventor(s) | 01 /
Sites, Richard L. 21 Warren Street Boylston, Massachusetts 01505 / US | 02 /
Witek, Richard T. 8 Silverbirch Lane Littleton, Massachusetts 01460 / US | [1992/02] | Representative(s) | Buchan, Ian Alexander, et al Eric Potter & Clarkson LLP Park View House 58 The Ropewalk Nottingham NG1 5DD4 / GB | [N/P] |
| Former [1999/41] | Buchan, Ian Alexander, et al Eric Potter & Clarkson, Park View House, 58 The Ropewalk Nottingham NG1 5DD4 / GB | ||
| Former [1999/38] | Signore, Robert, et al c/o BREVATOME 3, rue du Docteur Lanceraux 75008 Paris / FR | ||
| Former [1992/02] | Mongrédien, André, et al c/o SOCIETE DE PROTECTION DES INVENTIONS 25, rue de Ponthieu F-75008 Paris / FR | Application number, filing date | 91401770.2 | 27.06.1991 | [1992/02] | Priority number, date | US19900547619 | 29.06.1990 Original published format: US 547619 | [1992/02] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0465322 | Date: | 08.01.1992 | Language: | EN | [1992/02] | Type: | A3 Search report | No.: | EP0465322 | Date: | 19.11.1992 | Language: | EN | [1992/47] | Type: | B1 Patent specification | No.: | EP0465322 | Date: | 22.09.1999 | Language: | EN | [1999/38] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 28.09.1992 | Classification | IPC: | G06F9/308, G06F9/312, G06F9/315 | [1999/02] | CPC: |
G06F12/1027 (EP,US);
G06F9/30 (KR);
G06F9/30018 (EP,US);
G06F9/30021 (EP,US);
G06F9/30036 (EP,US);
G06F9/3004 (EP,US);
G06F9/30054 (EP,US);
G06F9/30072 (EP,US);
G06F9/30087 (EP,US);
G06F9/3816 (EP,US);
G06F9/3834 (EP,US);
G06F9/3836 (EP,US);
G06F9/3856 (EP,US);
G06F9/3858 (EP,US);
G06F9/3861 (EP,US);
G06F2212/652 (EP,US)
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| Former IPC [1992/02] | G06F9/308 | Designated contracting states | DE, FR, GB, NL [1992/02] | Title | German: | Registerhaltige Datenbearbeitung in einem Prozessor mit reduziertem Befehlssatz | [1992/02] | English: | In-register data manipulation in reduced instruction set processor | [1992/02] | French: | Manipulation de données en registre dans un processeur à jeu d'instructions réduit | [1999/03] |
| Former [1992/02] | Manipulation de données en registre dans un processeur à feu d'instructions réduit | Examination procedure | 03.03.1993 | Examination requested [1993/18] | 29.10.1996 | Despatch of a communication from the examining division (Time limit: M06) | 28.04.1997 | Reply to a communication from the examining division | 26.05.1997 | Despatch of a communication from the examining division (Time limit: M06) | 02.12.1997 | Reply to a communication from the examining division | 24.02.1998 | Despatch of a communication from the examining division (Time limit: M06) | 25.08.1998 | Reply to a communication from the examining division | 16.12.1998 | Despatch of communication of intention to grant (Approval: Yes) | 29.03.1999 | Communication of intention to grant the patent | 10.06.1999 | Fee for grant paid | 10.06.1999 | Fee for publishing/printing paid | Opposition(s) | 24.06.2000 | No opposition filed within time limit [2000/36] | Fees paid | Renewal fee | 25.06.1993 | Renewal fee patent year 03 | 27.05.1994 | Renewal fee patent year 04 | 26.05.1995 | Renewal fee patent year 05 | 28.05.1996 | Renewal fee patent year 06 | 27.05.1997 | Renewal fee patent year 07 | 26.05.1998 | Renewal fee patent year 08 | 04.06.1999 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | NL | 22.09.1999 | [2003/07] | Documents cited: | Search | [X]US3916388 (SHIMP EVERETT MONTAGUE, et al); | [A]WO8600433 (MOTOROLA INC [US]); | [X]EP0363176 (IBM [US]) | [A] - 1989 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS October 1989, CAMBRIDGE, MA, US pages 406 - 409 TORU SHIMIZU ET AL. 'A 32-Bit Microprocessor with High Performance Bit-Map Manipulation Instructions' | Examination | - J.L.HENNESSY ET AL.:"Computer architecture a quantitative approach", 11-12-89, MORGAN KAUFMANN, SAN MATEO, CA, US |