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EP0493251
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EP About this file: EP0493251
| EP0493251 - PLL synthesizer circuit [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 04.04.1997 Database last updated on 13.07.2024 | Most recent event Tooltip | 04.04.1997 | Application deemed to be withdrawn | published on 21.05.1997 [1997/21] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | For all designated states FUJITSU VLSI LIMITED 1844-2, Kozoji-cho 2-chome Kasugai-shi Aichi 487 / JP | [N/P] |
| Former [1992/27] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | ||
| For all designated states FUJITSU VLSI LIMITED 1844-2, Kozoji-cho 2-chome Kasugai-shi Aichi 487 / JP | Inventor(s) | 01 /
Saito, Shinji c/o Fujitsu VLSI Ltd., 1844-2, Kozoji-cho 2-chome Kasugai-shi, Aichi 487 / JP | 02 /
Kobayashi, Akira c/o Fujitsu VLSI Ltd., 1844-2, Kozoji-cho 2-chome Kasugai-shi, Aichi 487 / JP | [1992/27] | Representative(s) | Joly, Jean-Jacques, et al Cabinet Beau de Loménie 158, rue de l'Université 75340 Paris cedex 07 / FR | [N/P] |
| Former [1992/27] | Joly, Jean-Jacques, et al Cabinet Beau de Loménie 158, rue de l'Université F-75340 Paris Cédex 07 / FR | Application number, filing date | 91403533.2 | 24.12.1991 | [1992/27] | Priority number, date | JP19900406924 | 26.12.1990 Original published format: JP 40692490 | [1992/27] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0493251 | Date: | 01.07.1992 | Language: | EN | [1992/27] | Type: | A3 Search report | No.: | EP0493251 | Date: | 20.01.1993 | Language: | EN | [1993/03] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 30.11.1992 | Classification | IPC: | H03L7/183, H03L7/10 | [1992/27] | CPC: |
H03L7/00 (KR);
H03L7/0891 (EP,US);
H03L7/10 (EP,US);
H03L7/183 (EP,US)
| Designated contracting states | DE, FR, GB [1992/27] | Title | German: | PLL-Frequenzsynthetisierer | [1992/27] | English: | PLL synthesizer circuit | [1992/27] | French: | Synthétiseur de fréquence à PLL | [1992/27] | Examination procedure | 08.02.1993 | Examination requested [1993/14] | 13.04.1995 | Despatch of a communication from the examining division (Time limit: M04) | 22.08.1995 | Reply to a communication from the examining division | 13.09.1995 | Despatch of a communication from the examining division (Time limit: M06) | 21.03.1996 | Reply to a communication from the examining division | 11.07.1996 | Despatch of a communication from the examining division (Time limit: M04) | 22.11.1996 | Application deemed to be withdrawn, date of legal effect [1997/21] | 20.12.1996 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time [1997/21] | Fees paid | Renewal fee | 20.12.1993 | Renewal fee patent year 03 | 20.12.1994 | Renewal fee patent year 04 | 18.12.1995 | Renewal fee patent year 05 | Penalty fee | Additional fee for renewal fee | 31.12.1996 | 06 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JP58133042 ; | [A]US4937536 (REINHARDT VICTOR S [US], et al); | [A]EP0212810 (NEC CORP [JP]); | [A]US4792705 (OUYANG KENNETH W [US], et al) | [A] - PATENT ABSTRACTS OF JAPAN vol. 7, no. 243 (E-207)(1388) 28 October 1983 & JP-A-58 133 042 ( MATSUSHITA DENKI SANGYO KK ) 8 August 1983, & JP58133042 A 19830808 | [A] - ELECTRONICS LETTERS vol. 24, no. 17, 18 August 1988, ENAGE GB pages 1079 - 1080 R. C. DEN DULK: 'Digital fast acquisition method for phase-lock loops.' |