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EP0504714
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EP About this file: EP0504714
| EP0504714 - Semiconductor substrate having a SOI structure and method of producing the same [Right-click to bookmark this link] | Status | The application has been refused Status updated on 28.07.2000 Database last updated on 24.04.2024 | Most recent event Tooltip | 28.07.2000 | Refusal of application | published on 13.09.2000 [2000/37] | Applicant(s) | For all designated states SHIN-ETSU HANDOTAI COMPANY LIMITED 4-2, Marunouchi 1-Chome Chiyoda-ku Tokyo / JP | [N/P] |
| Former [1992/39] | For all designated states SHIN-ETSU HANDOTAI COMPANY LIMITED 4-2, Marunouchi 1-Chome Chiyoda-ku Tokyo / JP | Inventor(s) | 01 /
Abe, Takao 2-13-1 Isobe Annaka-shi, Gunma-ken / JP | 02 /
Nakazato, Yasuaki 1393 Ouaza Yashiro Koshoku-shi, Nagano-ken / JP | 03 /
Uchiyama, Atsuo 1393 Ouaza Yashiro Koshoku-shi, Nagano-ken / JP | [1992/39] | Representative(s) | Strehl Schübel-Hopf & Partner Maximilianstrasse 54 80538 München / DE | [N/P] |
| Former [1992/39] | Strehl Schübel-Hopf Groening & Partner Maximilianstrasse 54 D-80538 München / DE | Application number, filing date | 92104104.2 | 10.03.1992 | [1992/39] | Priority number, date | JP19910074420 | 15.03.1991 Original published format: JP 7442091 | [1992/39] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0504714 | Date: | 23.09.1992 | Language: | EN | [1992/39] | Type: | A3 Search report | No.: | EP0504714 | Date: | 02.10.1996 | [1996/40] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.08.1996 | Classification | IPC: | H01L21/76, H01L21/20 | [1992/39] | CPC: |
H01L21/76251 (EP,US);
H01L21/2007 (EP,US);
G02F1/13454 (EP,US);
Y10S438/977 (EP,US)
| Designated contracting states | DE, FR, GB [1992/39] | Title | German: | Halbleitersubstrat mit SOI-Struktur und Verfahren desser Herstellung | [1992/39] | English: | Semiconductor substrate having a SOI structure and method of producing the same | [1992/39] | French: | Substrat semi-conducteur du type SOI et procédé de fabrication | [1992/39] | Examination procedure | 13.03.1997 | Examination requested [1997/19] | 18.04.1997 | Despatch of a communication from the examining division (Time limit: M06) | 13.10.1997 | Reply to a communication from the examining division | 30.03.1999 | Despatch of a communication from the examining division (Time limit: M02) | 12.05.1999 | Reply to a communication from the examining division | 21.07.1999 | Despatch of communication of intention to grant (Approval: ) | 27.01.2000 | Despatch of communication that the application is refused, reason: formalities examination [2000/37] | 06.02.2000 | Application refused, date of legal effect [2000/37] | Fees paid | Renewal fee | 22.03.1994 | Renewal fee patent year 03 | 21.03.1995 | Renewal fee patent year 04 | 21.03.1996 | Renewal fee patent year 05 | 19.03.1997 | Renewal fee patent year 06 | 23.03.1998 | Renewal fee patent year 07 | 22.03.1999 | Renewal fee patent year 08 | Penalty fee | Additional fee for renewal fee | 31.03.2000 | 09 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] - HAISMA J ET AL, "Silicon-on-insulator wafer bonding-wafer thinning technological evaluations", INSPEC, INSTITUTE OF ELECTRICAL ENGINEERS, STEVENAGE, GB, XP002009190 [X] 1,2,4-6 * abstract * | [ ] - JAPANESE JOURNAL OF APPLIED PHYSICS, PART 1 (REGULAR PAPERS & SHORT NOTES), 1989, JAPAN, ISSN 0021-4922, vol. 28, no. 8, pages 1426 - 1443 |