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EP0510370
European procedure
Extract from the Register of European Patents
EP About this file: EP0510370
| EP0510370 - Semiconductor memory device having thin film transistor and method of producing the same [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 23.06.2000 Database last updated on 26.06.2024 | Most recent event Tooltip | 07.12.2007 | Lapse of the patent in a contracting state New state(s): IT | published on 09.01.2008 [2008/02] | Applicant(s) | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi Kanagawa 211 / JP | [N/P] |
| Former [1992/44] | For all designated states FUJITSU LIMITED 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa 211 / JP | Inventor(s) | 01 /
Ema, Taiji, c/o Fujitsu Limited 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa, 211 / JP | 02 /
Itabashi, Kazuo, c/o Fujitsu Limited 1015, Kamikodanaka, Nakahara-ku Kawasaki-shi, Kanagawa, 211 / JP | [1992/44] | Representative(s) | Schmidt-Evers, Jürgen, et al Mitscherlich PartmbB Patent- und Rechtsanwälte Postfach 33 06 09 80066 München / DE | [N/P] |
| Former [1993/19] | Schmidt-Evers, Jürgen, Dipl.-Ing., et al Patentanwälte Mitscherlich & Partner Postfach 33 06 09 D-80066 München / DE | ||
| Former [1992/44] | Schmidt-Evers, Jürgen, Dipl.-Ing. Patentanwälte Mitscherlich & Partner, Sonnenstrasse 33, Postfach 33 06 09 D-80066 München / DE | Application number, filing date | 92105146.2 | 25.03.1992 | [1992/44] | Priority number, date | JP19910085916 | 27.03.1991 Original published format: JP 8591691 | JP19910145940 | 18.06.1991 Original published format: JP 14594091 | [1992/44] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0510370 | Date: | 28.10.1992 | Language: | EN | [1992/44] | Type: | B1 Patent specification | No.: | EP0510370 | Date: | 25.08.1999 | Language: | EN | [1999/34] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 28.08.1992 | Classification | IPC: | H01L27/11, H01L21/82 | [1992/44] | CPC: |
H10B10/125 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1992/44] | Title | German: | Halbleiterspeicheranordnung mit einem Dünnschichttransistor und Herstellungsmethode für selben | [1992/44] | English: | Semiconductor memory device having thin film transistor and method of producing the same | [1992/44] | French: | Dispositif de mémoire semi-conductrice ayant un transistor à couche mince et procédé de fabrication associé | [1992/44] | Examination procedure | 30.12.1992 | Examination requested [1993/09] | 26.05.1995 | Despatch of a communication from the examining division (Time limit: M06) | 23.11.1995 | Reply to a communication from the examining division | 08.10.1996 | Despatch of a communication from the examining division (Time limit: M06) | 08.04.1997 | Reply to a communication from the examining division | 21.12.1998 | Despatch of communication of intention to grant (Approval: Yes) | 22.02.1999 | Communication of intention to grant the patent | 07.04.1999 | Fee for grant paid | 07.04.1999 | Fee for publishing/printing paid | Opposition(s) | 26.05.2000 | No opposition filed within time limit [2000/32] | Fees paid | Renewal fee | 30.03.1994 | Renewal fee patent year 03 | 30.03.1995 | Renewal fee patent year 04 | 29.03.1996 | Renewal fee patent year 05 | 27.03.1997 | Renewal fee patent year 06 | 30.03.1998 | Renewal fee patent year 07 | 30.03.1999 | Renewal fee patent year 08 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | FR | 25.08.1999 | IT | 25.08.1999 | GB | 25.03.2000 | [2008/02] |
| Former [2006/14] | FR | 25.08.1999 | |
| GB | 25.03.2000 | ||
| Former [2001/17] | FR | 21.01.2000 | |
| GB | 25.03.2000 | ||
| Former [2001/06] | FR | 21.01.2000 | Documents cited: | Search | [A]JP62169472 ; | [A]US4679171 (LOGWOOD DENNIS J [US], et al); | [A]US4764801 (MCLAUGHLIN KEVIN L [US], et al); | [A]US4853894 (YAMANAKA TOSHIAKI [JP], et al); | [Y]EP0365690 (SEIKO EPSON CORP [JP]); | [A]US4931410 (TOKUNAGA TAKAFUMI [JP], et al) | [Y] - INTERNATIONAL ELECTRON DEVICES MEETING December 1988, SAN FRANCISCO, CA, USA pages 48 - 51; T. YAMANAKA ET AL.: 'A 25 um2 NEW POLY-SI PMOS LOAD (PPL) SRAM CELL HAVING EXCELLENT SOFT ERROR IMMUNITY' | [A] - PATENT ABSTRACTS OF JAPAN vol. 12, no. 009 (E-572)12 January 1988 & JP-A-62 169 472 ( HITACHI ) 25 July 1987, & JP62169472 A 19870725 | [A] - IEEE JOURNAL OF SOLID-STATE CIRCUITS vol. 25, no. 1, February 1990, NEW YORK, USA pages 55 - 60; K. ISHIBASHI ET AL.: 'AN a-IMMUNE, 2-V SUPPLY VOLTAGE SRAM USING A POLYSILICON PMOS LOAD CELL' | [A] - SYMPOSIUM ON VLSI TECHNOLOGY June 1990, HONOLULU, JAPAN pages 19 - 20; A. O. ADAN ET AL.: 'A HALF-MICRON SRAM CELL USING A DOUBLE-GATED SELF-ALIGNED POLYSILICON PMOS THIN FILM TRANSISTOR (TFT) LOAD' | [A] - IEEE JOURNAL OF SOLID-STATE CIRCUITS vol. 24, no. 6, December 1989, NEW YORK, US pages 1708 - 1713; M. ANDO ET AL.: 'A 0.1-uA STANDBY CURRENT, GROUND-BOUNCE-IMMUNE 1-MBIT CMOS SRAM' |