-
EP0529217
European procedure
Extract from the Register of European Patents
EP About this file: EP0529217
| EP0529217 - Real time cache implemented by dual purpose on-chip memory [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 21.03.1997 Database last updated on 03.10.2024 | Most recent event Tooltip | 21.03.1997 | No opposition filed within time limit | published on 07.05.1997 [1997/19] | Applicant(s) | For all designated states MOTOROLA, INC. 1303 East Algonquin Road Schaumburg, IL 60196 / US | [1993/09] | Inventor(s) | 01 /
Baron, Nathan Haoren 22 Oranit / IL | 02 /
Marino, Paul Belinson Kfar Saba 44530 / IL | 03 /
Goren, Avner Remez 4 Ramat-Hasaron 47272 / IL | 04 /
Melanmed-Cohen, Eyal Hadvash 208/7 Jerusalem / IL | [1993/09] | Representative(s) | Dunlop, Hugh Christopher, et al Motorola European Intellectual Property Operations Midpoint Alencon Link Basingstoke, Hampshire RG21 7PL / GB | [N/P] |
| Former [1993/09] | Dunlop, Hugh Christopher, et al Motorola, European Intellectual Property, Midpoint, Alencon Link Basingstoke, Hampshire RG21 7PL / GB | Application number, filing date | 92109785.3 | 11.06.1992 | [1993/09] | Priority number, date | GB19910018312 | 24.08.1991 Original published format: GB 9118312 | [1993/09] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0529217 | Date: | 03.03.1993 | Language: | EN | [1993/09] | Type: | B1 Patent specification | No.: | EP0529217 | Date: | 15.05.1996 | Language: | EN | [1996/20] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 01.12.1992 | Classification | IPC: | G06F12/08 | [1993/09] | CPC: |
G06F12/0802 (EP,US);
G06F12/126 (EP,US);
G06F2212/2515 (EP,US)
| Designated contracting states | DE, FR, GB [1993/09] | Title | German: | Durch Doppelzweck-On-Chip-Speicher implementierter Echtzeit-Cachespeicher | [1993/09] | English: | Real time cache implemented by dual purpose on-chip memory | [1993/09] | French: | Antémémoire en temps réel constituée d'une mémoire puce à double usage | [1993/09] | Examination procedure | 25.08.1993 | Examination requested [1993/42] | 12.11.1993 | Despatch of a communication from the examining division (Time limit: M06) | 29.06.1994 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 25.07.1994 | Reply to a communication from the examining division | 04.07.1995 | Despatch of communication of intention to grant (Approval: Yes) | 21.11.1995 | Communication of intention to grant the patent | 01.03.1996 | Fee for grant paid | 01.03.1996 | Fee for publishing/printing paid | Opposition(s) | 18.02.1997 | No opposition filed within time limit [1997/19] | Request for further processing for: | 25.07.1994 | Request for further processing filed | 25.07.1994 | Full payment received (date of receipt of payment) Request granted | 09.08.1994 | Decision despatched | Fees paid | Renewal fee | 28.04.1994 | Renewal fee patent year 03 | 30.06.1995 | Renewal fee patent year 04 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]FR2519460 (NIPPON ELECTRIC CO [JP]); | [Y]WO8809008 (AMERICAN TELEPHONE & TELEGRAPH [US]); | [Y]EP0325420 (ADVANCED MICRO DEVICES INC [US]) | [A] - PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN : VLSI IN COMPUTERS AND PROCESSORS. 1989, IEEE, NEW YORK, US. pages 193 - 198 GROCHOWSKI ET AL. 'Issues in the implementation of the I486 cache and bus' |