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EP0525651
European procedure
Extract from the Register of European Patents
EP About this file: EP0525651
| EP0525651 - Package structure for one or more IC chips [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 10.08.2001 Database last updated on 06.07.2024 | Most recent event Tooltip | 10.08.2001 | No opposition filed within time limit | published on 26.09.2001 [2001/39] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [2000/41] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome, Minato-ku Tokyo / JP | ||
| Former [1993/05] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Miyazaki, Hirokazu c/o NEC Corporation, 7-1, Shiba 5-chome Minato-ku, Tokyo / JP | [1993/05] | Representative(s) | Vossius & Partner Patentanwälte Rechtsanwälte mbB Siebertstrasse 3 81675 München / DE | [N/P] |
| Former [1993/05] | VOSSIUS & PARTNER Postfach 86 07 67 D-81634 München / DE | Application number, filing date | 92112614.0 | 23.07.1992 | [1993/05] | Priority number, date | JP19910206224 | 24.07.1991 Original published format: JP 20622491 | [1993/05] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0525651 | Date: | 03.02.1993 | Language: | EN | [1993/05] | Type: | B1 Patent specification | No.: | EP0525651 | Date: | 11.10.2000 | Language: | EN | [2000/41] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.10.1992 | Classification | IPC: | H01L21/60, H01L23/10 | [1993/05] | CPC: |
H01L23/10 (EP);
H01L23/49816 (EP);
H01L23/5383 (EP);
H01L24/81 (EP);
H01L2224/16 (EP);
H01L2224/16225 (EP);
H01L2224/32245 (EP);
H01L2224/73253 (EP);
H01L2224/81801 (EP);
H01L2924/01004 (EP);
H01L2924/01005 (EP);
H01L2924/01006 (EP);
H01L2924/01013 (EP);
H01L2924/01023 (EP);
H01L2924/01033 (EP);
H01L2924/01043 (EP);
H01L2924/01047 (EP);
H01L2924/01056 (EP);
H01L2924/01058 (EP);
H01L2924/01059 (EP);
H01L2924/01061 (EP);
H01L2924/01066 (EP);
H01L2924/01076 (EP);
H01L2924/01077 (EP);
H01L2924/01082 (EP);
H01L2924/01088 (EP);
H01L2924/014 (EP);
H01L2924/12033 (EP);
H01L2924/14 (EP);
H01L2924/15312 (EP);
H01L2924/351 (EP)
(-)
| C-Set: |
H01L2924/12033, H01L2924/00 (EP);
H01L2924/351, H01L2924/00 (EP) | Designated contracting states | DE, FR, GB, NL [1993/05] | Title | German: | Packungsstruktur für integrierte Schaltungschips | [1993/05] | English: | Package structure for one or more IC chips | [1993/05] | French: | Structure d'empaquetage pour un ou plusieurs circuits intégrés | [1993/05] | Examination procedure | 17.11.1992 | Examination requested [1993/05] | 25.10.1994 | Despatch of a communication from the examining division (Time limit: M06) | 04.05.1995 | Reply to a communication from the examining division | 21.12.1995 | Despatch of a communication from the examining division (Time limit: M06) | 01.07.1996 | Reply to a communication from the examining division | 14.04.1997 | Despatch of a communication from the examining division (Time limit: M04) | 19.08.1997 | Reply to a communication from the examining division | 16.07.1999 | Despatch of communication of intention to grant (Approval: No) | 25.01.2000 | Despatch of communication of intention to grant (Approval: later approval) | 14.04.2000 | Communication of intention to grant the patent | 18.07.2000 | Fee for grant paid | 18.07.2000 | Fee for publishing/printing paid | Opposition(s) | 12.07.2001 | No opposition filed within time limit [2001/39] | Fees paid | Renewal fee | 29.07.1994 | Renewal fee patent year 03 | 28.07.1995 | Renewal fee patent year 04 | 30.07.1996 | Renewal fee patent year 05 | 30.07.1997 | Renewal fee patent year 06 | 29.07.1998 | Renewal fee patent year 07 | 28.07.1999 | Renewal fee patent year 08 | 31.07.2000 | Renewal fee patent year 09 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]JP02244661 ; | [Y]JP59088864 ; | [A]JP03016159 ; | [XP]JP03198367 ; | [Y]EP0260370 ; | [A]US3591839 | [X] - PATENT ABSTRACTS OF JAPAN vol. 14, no. 564 (E-1013) 14 December 1990 & JP-A-02 244 661 ( FUJITSU LTD ) 28 September 1990, & JP02244661 A 19900928 | [Y] - PATENT ABSTRACTS OF JAPAN vol. 8, no. 200 (E-266) 13 September 1984 & JP-A-59 088 864 ( MATSUSHITA DENKI SANGYO KK ) 22 May 1984, & JP59088864 A 19840522 | [A] - PATENT ABSTRACTS OF JAPAN vol. 15, no. 135 (E-1052) 4 April 1991 & JP-A-03 016 159 ( SHINKO ELECTRIC IND CO LTD ) 24 January 1991, & JP03016159 A 19910124 | [XP] - PATENT ABSTRACTS OF JAPAN vol. 15, no. 464 (E-1137) 25 November 1991 & JP-A-03 198 367 ( FUJITSU LTD ) 29 August 1991, & JP03198367 A 19910829 | Examination | - Microelectronics Packaging Handbook, Ed. R.Tummala et al., Van Nostrand 1989, pgs. 432-434,779-783,1183,1187 |