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Extract from the Register of European Patents

EP About this file: EP0543223

EP0543223 - Method of forming shallow junctions in field effect transistors [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  18.05.2001
Database last updated on 04.11.2024
Most recent event   Tooltip28.12.2002Lapse of the patent in a contracting state
New state(s): NL		published on 12.02.2003  [2003/07]
Applicant(s)For all designated states
SIEMENS AKTIENGESELLSCHAFT
Werner-von-Siemens-Str. 1
DE-80333 München / DE
[N/P]
Former [2000/29]For all designated states
SIEMENS AKTIENGESELLSCHAFT
Wittelsbacherplatz 2
80333 München / DE
Former [1993/21]For all designated states
SIEMENS AKTIENGESELLSCHAFT
Wittelsbacherplatz 2
D-80333 München / DE
Inventor(s)01 / Schwalke, Udo
Gewerbestr. 22
W-8251 Heldenstein / DE
02 / Zeller, Christoph
19 Thomas Avenue
Fishkill, NY 12524 / US
03 / Zeininger, Heinrich J.
Tannenstrasse 6
W-8501 Obermichelbach / DE
04 / Hänsch, Wilfried
RR 2 Box 2078
Charlotte, VT 05445 / US
[1993/21]
Application number, filing date92118906.404.11.1992
[1993/21]
Priority number, dateUS1991079095312.11.1991         Original published format: US 790953
[1993/21]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0543223
Date:26.05.1993
Language:EN
[1993/21]
Type: A3 Search report 
No.:EP0543223
Date:17.07.1996
[1996/29]
Type: B1 Patent specification 
No.:EP0543223
Date:19.07.2000
Language:EN
[2000/29]
Search report(s)(Supplementary) European search report - dispatched on:EP29.05.1996
ClassificationIPC:H01L21/225, H01L21/336, H01L21/265
[1993/21]
CPC:
H01L21/2652 (EP,US); H01L27/088 (KR); H01L21/2257 (EP,US);
H01L29/41783 (EP,US); H01L29/6659 (EP,US)
Designated contracting statesAT,   DE,   FR,   GB,   IT,   NL [1993/21]
TitleGerman:Verfahren zur Bildung von flachen Übergängen für Feldeffekttransistoren[1993/21]
English:Method of forming shallow junctions in field effect transistors[1993/21]
French:Méthode de formation de jonctions peu-profondes pour des transistors à effet de champ[1993/21]
Examination procedure09.01.1997Examination requested  [1997/11]
31.03.1998Despatch of a communication from the examining division (Time limit: M06)
10.09.1998Reply to a communication from the examining division
25.10.1999Despatch of communication of intention to grant (Approval: Yes)
20.12.1999Communication of intention to grant the patent
17.03.2000Fee for grant paid
17.03.2000Fee for publishing/printing paid
28.04.2000Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time
Opposition(s)20.04.2001No opposition filed within time limit [2001/27]
Request for further processing for:05.05.2000Request for further processing filed
05.05.2000Full payment received (date of receipt of payment)
Request granted
18.05.2000Decision despatched
Fees paidRenewal fee
18.11.1994Renewal fee patent year 03
17.11.1995Renewal fee patent year 04
18.11.1996Renewal fee patent year 05
20.11.1997Renewal fee patent year 06
17.11.1998Renewal fee patent year 07
18.11.1999Renewal fee patent year 08
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Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT19.07.2000
NL19.07.2000
DE20.10.2000
[2003/07]
Former [2002/13]AT19.07.2000
DE20.10.2000
Former [2001/17]AT19.07.2000
Documents cited:Search[X]EP0054259  (TOKYO SHIBAURA ELECTRIC CO [JP]) [X] 1,2,4,8,9,11,12,14,17,18,20-23,26-31 * page 19, line 10 - page 23, line 8; figures 6-8 *;
 [DA]US4788160  (HAVEMANN ROBERT H [US], et al) [DA] 1,2,8,9,11,12,17,18,20-22,26-31 * column 4, line 6 - column 6, line 35; figures 2-5 *;
 [A]EP0319213  (AMERICAN TELEPHONE & TELEGRAPH [US]) [A] 1,2,8,9,11,12,17,18,20-22,26-31* column 15, line 37 - column 16, line 54; figures 5-7 *;
 [A]  - PFIESTER J R, "A TIN STRAPPED POLYSILICON GATE COBALT SALICIDE CMOS PROCESS", INTERNATIONAL ELECTRON DEVICES MEETING, SAN FRANCISCO, DEC. 9 - 12, 1990, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19901209), no. -, pages 241 - 244, XP000279561 [A] 1,2,8,9,11,12,17,18,20-22,26-31 * abstract *
 [A]  - "PROCESS FOR LOW RESISTIVITY C0SI2 CONTACT TO VERY SHALLOW N-P JUNCTION", IBM TECHNICAL DISCLOSURE BULLETIN, (198909), vol. 32, no. 4A, pages 367 - 370, XP000039920 [A] 1,2,8,9,11,12,17,18,20-22,26-31 * page 369; figure 3 *
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.