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EP0548585
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EP About this file: EP0548585
| EP0548585 - Clocking mechanism for delay, short path and stuck-at testing [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 22.03.1995 Database last updated on 11.09.2024 | Most recent event Tooltip | 22.03.1995 | Withdrawal of application | published on 10.05.1995 [1995/19] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1993/26] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Koenemann, Bernd Karl Ferdinand 21 Pellbridge Drive Hopewell Junction, New York 12533 / US | 02 /
McAnney, William Howard RR No. 1, Box 276, Waterbury Hill Road La Grangeville, New York 12540 / US | 03 /
Shulman, Mark Lee 23 Hollow Ridge Road Staatsburg, New York 12580 / US | [1993/26] | Representative(s) | Jost, Ottokarl IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht 70548 Stuttgart / DE | [N/P] |
| Former [1993/26] | Jost, Ottokarl, Dipl.-Ing. IBM Deutschland Informationssysteme GmbH, Patentwesen und Urheberrecht D-70548 Stuttgart / DE | Application number, filing date | 92120279.2 | 27.11.1992 | [1993/26] | Priority number, date | US19910811205 | 20.12.1991 Original published format: US 811205 | [1993/26] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0548585 | Date: | 30.06.1993 | Language: | EN | [1993/26] | Type: | A3 Search report | No.: | EP0548585 | Date: | 18.01.1995 | Language: | EN | [1995/03] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.12.1994 | Classification | IPC: | G06F11/26 | [1993/26] | CPC: |
G01R31/31858 (EP,US);
G01R31/318552 (EP,US)
| Designated contracting states | DE, FR, GB [1993/26] | Title | German: | Takteinrichtung zum Prüfen von Verzögerung, Kurzweg und Ständig-auf | [1993/26] | English: | Clocking mechanism for delay, short path and stuck-at testing | [1993/26] | French: | Dispositif d'horloge pour le test de retard, de trajet court et de tenu sur | [1993/26] | File destroyed: | 03.10.2001 | Examination procedure | 21.10.1993 | Examination requested [1993/51] | 16.03.1995 | Application withdrawn by applicant [1995/19] | Fees paid | Renewal fee | 25.11.1994 | Renewal fee patent year 03 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0130610 (IBM [US]) [A] 1-4 * the whole document * | [X] - O. BULA ET AL., "Gross delay defect evaluation for a CMOS logic design system product", IBM JOURNAL OF RESEARCH AND DEVELOPMENT, NEW YORK US, (199003), vol. 34, no. 2/3, pages 325 - 337, XP000138146 [X] 1-4 * page 327, column R, line 3 - page 328, column R, line 9; figures 1,2 * | [X] - F. MOTIKA ET AL., "A logic chip delay-test method based on system timing", IBM JOURNAL OF RESEARCH AND DEVELOPMENT, NEW YORK US, (199003), vol. 34, no. 2/3, pages 299 - 312, XP000138144 [X] 1-4 * page 305, column R - page 306, column L; figure 10 * |