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EP0588032
European procedure
Extract from the Register of European Patents
EP About this file: EP0588032
| EP0588032 - Process for forming implanted regions with lowered channeling risk on semiconductors [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.08.2002 Database last updated on 24.04.2024 | Most recent event Tooltip | 30.08.2002 | No opposition filed within time limit | published on 16.10.2002 [2002/42] | Applicant(s) | For all designated states STMicroelectronics Srl Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | [N/P] |
| Former [1998/35] | For all designated states STMicroelectronics S.r.l. Via C. Olivetti, 2 20041 Agrate Brianza (Milano) / IT | ||
| Former [1994/12] | For all designated states SGS-THOMSON MICROELECTRONICS S.r.l. Via C. Olivetti, 2 I-20041 Agrate Brianza (Milano) / IT | Inventor(s) | 01 /
Zaccherini, Chiara Via Pinturicchio 21 I-20133 Milano / IT | [1994/12] | Representative(s) | Botti, Mario Botti & Ferrari S.p.A. Via Cappellini, 11 20124 Milano / IT | [N/P] |
| Former [1999/17] | Botti, Mario Botti & Ferrari S.r.l. Via Locatelli, 5 20124 Milano / IT | ||
| Former [1994/12] | Checcacci, Giorgio PORTA, CHECCACCI & BOTTI s.r.l. Viale Sabotino, 19/2 I-20135 Milano / IT | Application number, filing date | 93111968.9 | 27.07.1993 | [1994/12] | Priority number, date | IT1992MI02003 | 19.08.1992 Original published format: IT MI922003 | [1994/12] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0588032 | Date: | 23.03.1994 | Language: | EN | [1994/12] | Type: | A3 Search report | No.: | EP0588032 | Date: | 31.01.1996 | [1996/05] | Type: | B1 Patent specification | No.: | EP0588032 | Date: | 24.10.2001 | Language: | EN | [2001/43] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 15.12.1995 | Classification | IPC: | H01L21/3215, H01L21/265, H01L21/02 | [2000/39] | CPC: |
H01L28/20 (EP,US);
H01L21/32155 (EP,US);
H10B10/00 (EP,US);
H10B10/15 (EP,US)
|
| Former IPC [1995/51] | H01L21/3215, H01L21/265 | ||
| Former IPC [1994/12] | H01L21/265, H01L21/3215 | Designated contracting states | DE, FR, GB [1994/12] | Title | German: | Verfahren zur Bildung implantierter Gebiete mit einem reduzierten Channeling-Risiko in Halbleitern | [1994/12] | English: | Process for forming implanted regions with lowered channeling risk on semiconductors | [1994/12] | French: | Procédé de formation de régions implantées, présentant un risque réduit de canalisation, dans des semiconducteurs | [1994/12] | Examination procedure | 28.08.1993 | Loss of particular rights, legal effect: Claims | 06.12.1993 | Despatch of communication of loss of particular rights: Claims {1} | 19.09.1996 | Examination requested [1996/47] | 30.09.1998 | Despatch of a communication from the examining division (Time limit: M06) | 07.04.1999 | Reply to a communication from the examining division | 27.10.2000 | Despatch of communication of intention to grant (Approval: Yes) | 21.11.2000 | Communication of intention to grant the patent | 07.02.2001 | Fee for grant paid | 07.02.2001 | Fee for publishing/printing paid | Opposition(s) | 25.07.2002 | No opposition filed within time limit [2002/42] | Fees paid | Renewal fee | 20.07.1995 | Renewal fee patent year 03 | 26.07.1996 | Renewal fee patent year 04 | 24.07.1997 | Renewal fee patent year 05 | 21.07.1998 | Renewal fee patent year 06 | 26.07.1999 | Renewal fee patent year 07 | 28.07.2000 | Renewal fee patent year 08 | 26.07.2001 | Renewal fee patent year 09 | Penalty fee | Penalty fee Rule 85b EPC 1973 | 11.09.1996 | M01 Fee paid on 19.09.1996 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XA]US4489104 (LEE MING-KWANG [TW]) [X] 10 * column 2, line 51 - column 3, line 38; figures 2A-2D * [A] 1-9; | [A]EP0193117 (TOSHIBA KK [JP]) [A] 1-3,5-10 * column 2, line 11 - line 22; figure 1A * * column 2, line 31 - line 34 * * column 3, line 12 - line 35 * * column 4, line 13 - line 35; figures 2A-2D ** column 5, line 27 - column 6, line 13 *; | [XA]US4637836 (FLATLEY DORIS W [US], et al) [X] 10 * column 1, line 9 - line 38 * * column 1, line 47 - column 2, line 16 * * column 2, line 23 - line 49 * * column 3, line 61 - column 4, line 3 * [A] 1-9; | [XA]US5005068 (IKEDA SHUJI [JP], et al) [X] 10 * column 1, line 8 - line 22 * * column 5, line 21 - line 54; figures 2A, 3, 5 * [A] 1,2,4-7,9; | [PXA]EP0524025 (SGS THOMSON MICROELECTRONICS [US]) [PX] 1-8,10 * column 1, line 1 - line 4 * * column 2, line 33 - line 39 * * column 3, line 12 - column 4, line 2; figures 1A-1C * [PA] 9 | [A] - SANG-JIK KWON ET AL., "As+-preamorphization method for shallow P+-n junction formation.", JAPANESE JOURNAL OF APPLIED PHYSICS, TOKYO JP, vol. 29, no. 12, pages L2326 - L2328 [A] 1-3,5-9 * page L2326, column L; figures 1,2 * * page L2328, paragraph 4 * |