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EP0562881
European procedure
Extract from the Register of European Patents
EP About this file: EP0562881
| EP0562881 - Wired-OR logic circuit [Right-click to bookmark this link] | |||
| Former [1993/39] | Wired-or logic circuit | ||
| [1998/33] | Status | No opposition filed within time limit Status updated on 18.06.1999 Database last updated on 06.07.2024 | Most recent event Tooltip | 18.06.1999 | No opposition filed within time limit | published on 04.08.1999 [1999/31] | Applicant(s) | For all designated states NEC Corporation 7-1, Shiba 5-chome Minato-ku Tokyo 108-8001 / JP | [N/P] |
| Former [1993/39] | For all designated states NEC CORPORATION 7-1, Shiba 5-chome Minato-ku Tokyo / JP | Inventor(s) | 01 /
Nakaigawa, Sachio c/o NEC Corporation 7-1, Shiba 5-chome, Minato-ku Tokyo / JP | [1993/39] | Representative(s) | Moir, Michael Christopher, et al Mathys & Squire LLP 120 Holborn London EC1N 2SQ / GB | [N/P] |
| Former [1993/39] | Moir, Michael Christopher, et al Mathys & Squire 100 Grays Inn Road London WC1X 8AL / GB | Application number, filing date | 93302379.8 | 26.03.1993 | [1993/39] | Priority number, date | JP19920067847 | 26.03.1992 Original published format: JP 6784792 | [1993/39] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0562881 | Date: | 29.09.1993 | Language: | EN | [1993/39] | Type: | A3 Search report | No.: | EP0562881 | Date: | 23.02.1994 | Language: | EN | [1994/08] | Type: | B1 Patent specification | No.: | EP0562881 | Date: | 12.08.1998 | Language: | EN | [1998/33] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 03.01.1994 | Classification | IPC: | H03K19/082, H03K19/00, H03K19/003, H03K19/018, H04L25/08, H03K19/086 | [1994/07] | CPC: |
H03K19/086 (EP,US);
H03K19/082 (EP,US)
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| Former IPC [1993/39] | H03K19/082 | Designated contracting states | DE, FR, GB [1993/39] | Title | German: | ODER-Verdrahtete logische Schaltung | [1998/33] | English: | Wired-OR logic circuit | [1998/33] | French: | Circuit logique OU-câblé | [1998/33] |
| Former [1993/39] | Verdrahtete logische ODER-Schaltung | ||
| Former [1993/39] | Wired-or logic circuit | ||
| Former [1993/39] | Circuit logique ou câblé | Examination procedure | 05.02.1994 | Examination requested [1994/14] | 06.02.1996 | Despatch of a communication from the examining division (Time limit: M06) | 05.08.1996 | Reply to a communication from the examining division | 17.11.1997 | Despatch of communication of intention to grant (Approval: Yes) | 28.01.1998 | Communication of intention to grant the patent | 10.03.1998 | Fee for grant paid | 10.03.1998 | Fee for publishing/printing paid | Opposition(s) | 13.05.1999 | No opposition filed within time limit [1999/31] | Fees paid | Renewal fee | 29.03.1995 | Renewal fee patent year 03 | 25.03.1996 | Renewal fee patent year 04 | 21.03.1997 | Renewal fee patent year 05 | 23.03.1998 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]JPS56107641 ; | [A]JPS63200617 ; | [A]JPS5947842 ; | [A]JPH01147915 ; | [X]US5093587 (ZBINDEN TERRY B [US]) [X] 1,2 * column 4, line 40 - column 6, line 2; figures 9-11 * | [A] - PATENT ABSTRACTS OF JAPAN, (19811120), vol. 5, no. 181, Database accession no. (E - 83)<853>, & JP56107641 A 19810826 (NIPPON DENKI K.K.) [A] 3 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19881219), vol. 12, no. 486, Database accession no. (E - 695), & JP63200617 A 19880818 (MITSUBISHI ELECTRIC CORP.) [A] 1 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19840628), vol. 8, no. 139, Database accession no. (E - 253), & JP59047842 A 19840317 (NIPPON DENKI K.K.) [A] 1 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19890908), vol. 13, no. 407, Database accession no. (E - 818), & JP01147915 A 19890609 (HITACHI LTD) [A] 1 * abstract * |