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Extract from the Register of European Patents

EP About this file: EP0644549

EP0644549 - Method of flash writing with small operation current and semiconductor memory circuit according to the method [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  05.04.2002
Database last updated on 13.09.2024
Most recent event   Tooltip05.04.2002No opposition filed within time limitpublished on 22.05.2002  [2002/21]
Applicant(s)For all designated states
NEC Corporation
7-1, Shiba 5-chome Minato-ku
Tokyo 108-8001 / JP
[N/P]
Former [2001/22]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
Former [1995/12]For all designated states
NEC CORPORATION
7-1, Shiba 5-chome Minato-ku
Tokyo / JP
Inventor(s)01 / Kusakari, Takashi, c/o NEC Corporation
7-1, Shiba 5-chome, Minato-ku
Tokyo / JP
[1995/12]
Representative(s)Baronetzky, Klaus, et al
Splanemann
Patentanwälte Partnerschaft
Rumfordstrasse 7
80469 München / DE
[N/P]
Former [1995/12]Baronetzky, Klaus, Dipl.-Ing., et al
Patentanwälte Dipl.-Ing. R. Splanemann, Dr. B. Reitzner, Dipl.-Ing. K. Baronetzky Tal 13
D-80331 München / DE
Application number, filing date94113837.203.09.1994
[1995/12]
Priority number, dateJP1993022839214.09.1993         Original published format: JP 22839293
[1995/12]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0644549
Date:22.03.1995
Language:EN
[1995/12]
Type: A3 Search report 
No.:EP0644549
Date:26.06.1996
[1996/26]
Type: B1 Patent specification 
No.:EP0644549
Date:30.05.2001
Language:EN
[2001/22]
Search report(s)(Supplementary) European search report - dispatched on:EP08.05.1996
ClassificationIPC:G11C7/00, G11C11/407
[1996/24]
CPC:
G11C7/20 (EP,US); G11C7/22 (EP,KR,US); G11C7/06 (KR);
G11C7/1078 (KR)
Former IPC [1995/12]G11C7/00
Designated contracting statesDE,   FR,   GB,   IT [1995/12]
TitleGerman:Flash-Schreibeverfahren mit niedrigem Strom und Halbleiterspeicherschaltung nach einem solchen Verfahren[2001/22]
English:Method of flash writing with small operation current and semiconductor memory circuit according to the method[1995/12]
French:Méthode d'écriture en mode flash à courant d'opération faible et circuit de mémoire à semi-conducteurs selon cette méthode[1995/12]
Former [1995/12]Flash-Schreibeverfahren mit niedrigem Strom und Halbleiterspeicherschaltung nach einem solchem Verfahren
Examination procedure27.12.1996Examination requested  [1997/10]
18.11.1998Despatch of a communication from the examining division (Time limit: M04)
22.03.1999Reply to a communication from the examining division
01.04.1999Despatch of a communication from the examining division (Time limit: M04)
02.08.1999Reply to a communication from the examining division
14.08.2000Despatch of communication of intention to grant (Approval: Yes)
27.11.2000Communication of intention to grant the patent
21.02.2001Fee for grant paid
21.02.2001Fee for publishing/printing paid
Opposition(s)01.03.2002No opposition filed within time limit [2002/21]
Fees paidRenewal fee
02.08.1996Renewal fee patent year 03
22.08.1997Renewal fee patent year 04
19.08.1998Renewal fee patent year 05
06.08.1999Renewal fee patent year 06
04.08.2000Renewal fee patent year 07
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Documents cited:Search[A]US4823322  (MIYATAKE HIDESHI [JP], et al) [A] 1-7 * column 4, line 29 - column 5, line 60; figures 1,5 *;
 [A]US4873672  (ETOH JUN [JP], et al) [A] 4* column 8, line 42 - column 10, line 7; figures 8-11 *;
 [A]EP0337172  (TOSHIBA KK [JP]) [A] 1-7 * column 3, line 11 - column 8, line 5; figures 2-7 *;
 [DA]EP0352572  (NEC CORP [JP]) [DA] 1-7 * column 6, line 30 - column 10, line 34; figures 4-6 *
by applicantEP0337172
 JPH0229987
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.