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EP0606979
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EP About this file: EP0606979
| EP0606979 - CMOS multi-tap digital delay line with non-inverting taps [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 18.10.1996 Database last updated on 29.06.2024 | Most recent event Tooltip | 18.10.1996 | Application deemed to be withdrawn | published on 04.12.1996 [1996/49] | Applicant(s) | For all designated states NATIONAL SEMICONDUCTOR CORPORATION 2900 Semiconductor Drive, P.O. Box 58090 Santa Clara California 95052-8090 / US | [N/P] |
| Former [1994/29] | For all designated states NATIONAL SEMICONDUCTOR CORPORATION 2900 Semiconductor Drive, P.O. Box 58090 Santa Clara, California 95052-8090 / US | Inventor(s) | 01 /
Llewellyn, William D. 1484 Proud Drive San Jose, California 95132 / US | [1994/29] | Representative(s) | Horton, Andrew Robert Grant, et al Bowles Horton Felden House Dower Mews High Street Berkhamsted, Hertfordshire HP4 2BL / GB | [N/P] |
| Former [1994/29] | Horton, Andrew Robert Grant, et al BOWLES HORTON Felden House Dower Mews High Street Berkhamsted Hertfordshire HP4 2BL / GB | Application number, filing date | 94300061.2 | 06.01.1994 | [1994/29] | Priority number, date | US19930004042 | 15.01.1993 Original published format: US 4042 | [1994/29] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0606979 | Date: | 20.07.1994 | Language: | EN | [1994/29] | Type: | A3 Search report | No.: | EP0606979 | Date: | 13.09.1995 | Language: | EN | [1995/37] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 24.07.1995 | Classification | IPC: | H03K5/13, H03H11/26 | [1994/29] | CPC: |
H03K5/131 (EP,US);
H03K5/133 (EP,US);
H03L7/085 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1994/29] | Title | German: | Mit mehreren nicht-invertierenden Abgriffen versehene, digitale CMOS-Verzögerungsleitung | [1994/29] | English: | CMOS multi-tap digital delay line with non-inverting taps | [1994/29] | French: | Ligne à retard numérique CMOS à prises multiples non inversantes | [1994/29] | File destroyed: | 13.09.2003 | Examination procedure | 14.03.1996 | Application deemed to be withdrawn, date of legal effect [1996/49] | 05.07.1996 | Despatch of communication that the application is deemed to be withdrawn, reason: examination fee not paid in time [1996/49] | Fees paid | Renewal fee | 08.01.1996 | Renewal fee patent year 03 | Penalty fee | Penalty fee Rule 85b EPC 1973 | 23.04.1996 | M01 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]DE4140564 (SONY CORP [JP]) [A] 1,3,4,6,13 * page 4, line 1 - line 46 * * page 5, line 55 - page 6, line 37; figures 1,10,11 *; | [A]EP0091375 (FAIRCHILD CAMERA INSTR CO [US]) [A] 1,3,4,6,13 * page 8, line 14 - page 9, line 7; figure 3 *; | [A]EP0317758 (TEKTRONIX INC [US]) [A] 1,3,4,6,13 * column 3, line 17 - column 4, line 57; figure 1 * | [A] - K. SAKAMOTO ET AL., "A digitally programmable delay chip with picosecond resolution.", PROCEEDINGS OF THE 1989 BIPOLAR CIRCUITS AND TECHNOLOGY MEETING, MINNEAPOLIS, MN, US, (19890918), pages 295 - 297 [A] 1,3,4,6,13 * page 295, line 7 - line 25; figure 1 * | [A] - V. RAO, "Phase shifter varies clock-generator output.", ELECTRONIC DESIGN, WASECA, MN, DENVILLE, NJ, US, (198302), vol. 31, no. 4, pages 153 - 154 [A] 1,6,13 * the whole document * |