Extract from the Register of European Patents

EP About this file: EP0655679

EP0655679 - Method and apparatus for controlling instruction in pipeline processor [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  06.12.2002
Database last updated on 11.04.2026
Most recent event   Tooltip06.12.2002No opposition filed within time limitpublished on 22.01.2003  [2003/04]
Applicant(s)For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku Kawasaki-shi
Kanagawa 211 / JP
[N/P]
Former [1995/22]For all designated states
FUJITSU LIMITED
1015, Kamikodanaka, Nakahara-ku
Kawasaki-shi, Kanagawa 211 / JP
Inventor(s)01 / Inoue, Aiichiro, c/o Fujitsu Limited
1015 Kamikodanaka, Nakahara-ku
Kawasaki-shi, Kanagawa 211 / JP
[1995/22]
Representative(s)Billington, Lawrence Emlyn, et al
Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn
London WC1V 7JH / GB
[N/P]
Former [1995/22]Billington, Lawrence Emlyn, et al
HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane
London WC2A 1AT / GB
Application number, filing date94306879.120.09.1994
[1995/22]
Priority number, dateJP1993029694026.11.1993         Original published format: JP 29694093
[1995/22]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0655679
Date:31.05.1995
Language:EN
[1995/22]
Type: A3 Search report 
No.:EP0655679
Date:28.06.1995
Language:EN
[1995/26]
Type: B1 Patent specification 
No.:EP0655679
Date:30.01.2002
Language:EN
[2002/05]
Search report(s)(Supplementary) European search report - dispatched on:EP15.05.1995
ClassificationIPC:G06F9/38
[1995/22]
CPC:
G06F9/3806 (EP,US)
Designated contracting statesDE,   FR,   GB [1995/22]
TitleGerman:Verfahren und Vorrichtung zur Befehlsteuerung in einem Pipelineprozessor[1995/22]
English:Method and apparatus for controlling instruction in pipeline processor[1995/22]
French:Procédé et dispositif pour commande d'instructions dans un processeur en pipeline[1995/22]
Examination procedure21.12.1995Examination requested  [1996/08]
02.06.1999Despatch of a communication from the examining division (Time limit: M04)
06.10.1999Reply to a communication from the examining division
11.02.2000Despatch of a communication from the examining division (Time limit: M06)
14.08.2000Reply to a communication from the examining division
02.05.2001Despatch of communication of intention to grant (Approval: Yes)
19.07.2001Communication of intention to grant the patent
15.10.2001Fee for grant paid
15.10.2001Fee for publishing/printing paid
Opposition(s)31.10.2002No opposition filed within time limit [2003/04]
Fees paidRenewal fee
26.09.1996Renewal fee patent year 03
23.09.1997Renewal fee patent year 04
25.09.1998Renewal fee patent year 05
22.09.1999Renewal fee patent year 06
25.09.2000Renewal fee patent year 07
26.09.2001Renewal fee patent year 08
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Documents cited:Search[Y] EP0109655  (NEC CORP et al.) [Y] 1-3,6-12 * the whole document *
 [Y] EP0402524  (NEC CORP et al.) [Y] 1-3 * column 4, line 6 - column 2, line 3 *
 [Y] US4200927  (HUGHES JEFFREY F et al.) [Y] 6-12 * summary ; column 3, line 48 - column 4, line 27 ; column 5, lines 29-43 ; column * * 11, line 55 - column 12, line 46 ; column 13, line 34 - column 18, line 3 *
 [A] WO9301545  (SEIKO EPSON CORP et al.) [A] 5,6,9-12 * pages 14-35 *
 [A] EP0355069  (EVANS & SUTHERLAND COMPUTER CO et al.) [A] 4-6,9,11,12 * column 3, lines 20-35 ; column 3, line 55 - column 4, line 34; column 5, line 65 * * - column 6, line 11 *
ExaminationEP0179245
   Reducing the Branch Penalty in Pipelined Processors, David J. Lilja, Computer, July 1988, No 7, New York, NY, USA
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