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EP0653708
European procedure
Extract from the Register of European Patents
EP About this file: EP0653708
| EP0653708 - Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 15.06.2001 Database last updated on 19.07.2024 | Most recent event Tooltip | 15.06.2001 | No opposition filed within time limit | published on 01.08.2001 [2001/31] | Applicant(s) | For all designated states Hitachi, Ltd. 6, Kanda Surugadai 4-chome Chiyoda-ku Tokyo 101 / JP | [N/P] |
| Former [2000/33] | For all designated states Hitachi, Ltd. 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 101 / JP | ||
| Former [1995/20] | For all designated states HITACHI, LTD. 6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 101 / JP | Inventor(s) | 01 /
Suzuki, Shoji 17-1-202, Moriyama-cho 3-chome Hitachi-shi, Ibaraki 316 / JP | 02 /
Sato, Yoshimichi Yuuhou-ryo 34, 20-3, Ayukawa-cho 6-chome Hitachi-shi, Ibaraki 316 / JP | 03 /
Tashiro, Korefumi 5-1, Oomika-cho 6-chome Hitachi-shi, Ibaraki 319-12 / JP | 04 /
Bekki, Keisuke 17-2-503, Moriyama-cho 3-chome Hitachi-shi, Ibaraki 316 / JP | 05 /
Sato, Hiroshi 2920-114, Nawatari Katsuta-shi, Ibaraki 312 / JP | 06 /
Nohmi, Makoto Tsukubadai Terasu 103, 663, Ichige Katsuta-shi, Ibaraki 312 / JP | [1995/20] | Representative(s) | Calderbank, Thomas Roger, et al Mewburn Ellis LLP City Tower 40 Basinghall Street London EC2V 5DE / GB | [N/P] |
| Former [1995/20] | Calderbank, Thomas Roger, et al MEWBURN ELLIS York House 23 Kingsway London WC2B 6HP / GB | Application number, filing date | 94307483.1 | 12.10.1994 | [1995/20] | Priority number, date | JP19930258013 | 15.10.1993 Original published format: JP 25801393 | JP19940027664 | 25.02.1994 Original published format: JP 2766494 | [1995/20] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0653708 | Date: | 17.05.1995 | Language: | EN | [1995/20] | Type: | A3 Search report | No.: | EP0653708 | Date: | 02.08.1995 | Language: | EN | [1995/31] | Type: | B1 Patent specification | No.: | EP0653708 | Date: | 16.08.2000 | Language: | EN | [2000/33] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 16.06.1995 | Classification | IPC: | G06F11/16, G06F11/00, G06F11/20 | [1995/29] | CPC: |
G06F11/0763 (EP,US);
G05B9/03 (EP,US);
G06F11/085 (EP,US);
G06F11/1695 (EP,US);
G06F11/188 (EP,US);
G06F11/2023 (EP,US);
G06F11/2035 (EP,US);
G06F11/2215 (EP,US);
G06F11/008 (EP,US);
|
| Former IPC [1995/20] | G06F11/16 | Designated contracting states | DE, FR, GB [1995/20] | Title | German: | Logischer Schaltkreis mit Fehlernachweisfunktion, Verfahren zum Verwalten von Betriebsmitteln und fehlertolerantes System zu seiner Anwendung | [1995/20] | English: | Logic circuit having error detection function, redundant resource management method, and fault tolerant system using it | [1995/20] | French: | Circuit logique avec fonction de détection d'erreurs, procédé de gestion des ressources redoudantes et système tolérant des fautes pour sa mise en oeuvre | [1995/20] | Examination procedure | 02.11.1994 | Examination requested [1995/20] | 23.04.1999 | Despatch of a communication from the examining division (Time limit: M04) | 13.08.1999 | Reply to a communication from the examining division | 29.09.1999 | Despatch of communication of intention to grant (Approval: Yes) | 10.02.2000 | Communication of intention to grant the patent | 02.05.2000 | Fee for grant paid | 02.05.2000 | Fee for publishing/printing paid | Divisional application(s) | EP00100479.5 / EP1016968 | EP01120968.1 / EP1168178 | Opposition(s) | 17.05.2001 | No opposition filed within time limit [2001/31] | Fees paid | Renewal fee | 22.10.1996 | Renewal fee patent year 03 | 21.10.1997 | Renewal fee patent year 04 | 21.10.1998 | Renewal fee patent year 05 | 22.10.1999 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0148995 (SIEMENS AG [DE]) [A] 1,7,8,10-12 * abstract * * page 4, line 19 - page 5, line 7 * * page 5, line 25 - page 6, line 5 *; | [A]GB2219865 (INTEL CORP [US]) [A] 1,7,8,10-12 * abstract * * page 7, line 16 - page 8, line 35 * * page 9, line 23 - line 26 * * figure 1 *; | [X]US4933838 (ELROD STEVEN E [US]) [X] 13* column 9, line 54 - column 10, line 49 *; | [XA] - MORIKAZU TAKEGAKI ET AL, "THE DIFFUSION MODEL BASED TASK REMAPPING FOR DISTRIBUTED REAL-TIME SYSTEMS", PROCEEDINGS OF THE REAL TIME SYSTEMS SYMPOSIUM, SAN ANTONIO, DEC. 4 - 6, 1991, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19911204), no. SYMP., pages 2 - 11, XP000337134 [X] 13 * abstract * * page 5, column L, line 11 - page 6, column R, line 6 * [A] 14-17 | [A] - CUYVERS R ET AL, "A KERNEL FOR MULTI-LEVEL FAULT-TOLERANT MULTIPROCESSING1", PROCEEDINGS OF SOUTHEASTCON, WILLIAMSBURG, APRIL 7 - 10, 1991, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19910101), vol. 1, pages 248 - 252, XP000286858 [A] 13,14-17 * page 249, column L, line 27 - line 45 * * page 250, column R, line 6 - line 28 * * page 251, column R, line 23 - line 46 * DOI: http://dx.doi.org/10.1109/SECON.1991.147747 | [XA] - ISHFAQ AHMAD ET AL, "FAULT-TOLERANT TASK MANAGEMENT AND LOAD RE-DISTRIBUTION ON MASSIVELY PARALLEL HYPERCUBE SYSTEMS", PROCEEDINGS OF THE SUPERCOMPUTING CONFERENCE, MINNEAPOLIS, NOV. 16 - 20, 1992, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, XP000358040 [X] 13 * abstract * * page 754, column R, line 15 - line 20 * [A] 14,15 |