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EP0649093
European procedure
Extract from the Register of European Patents
EP About this file: EP0649093
| EP0649093 - Logic gate testing [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.01.1999 Database last updated on 15.06.2024 | Most recent event Tooltip | 08.01.1999 | No opposition filed within time limit | published on 24.02.1999 [1999/08] | Applicant(s) | For all designated states Holness, Peter John 26 Molewood Road Near Bengeo Hertford / GB | [1995/22] |
| Former [1995/16] | For all designated states BRITISH AEROSPACE PUBLIC LIMITED COMPANY Warwick House, P.O. Box 87, Farnborough Aerospace Centre Farnborough, Hants. GU14 6YU / GB | Inventor(s) | 01 /
Holness, Peter J., British Aerospace Defence Ltd. Six Hills Way, Stevenage Hertfordshire, SG1 2DA / GB | 02 /
Patel, Mukesh, c/o Jayresh R Patel 7413 Southwick Drive Garland Texas Zip Code 75044 / US | [1995/16] | Representative(s) | Gallafent, Antony Xavier, et al Urquhart-Dykes & Lord LLP Churchill House Churchill Way Cardiff CF10 2HH / GB | [N/P] |
| Former [1996/11] | Gallafent, Antony Xavier, et al Gallafent & Co., 9 Staple Inn London WC1V 7QH / GB | ||
| Former [1995/23] | (deleted) | ||
| Former [1995/16] | Potts, Susan Patricia, et al British Aerospace plc Lancaster House P.O. Box 87, Farnborough Aerospace Centre Farnborough, Hants. GU14 6YU / GB | Application number, filing date | 94307532.5 | 13.10.1994 | [1995/16] | Priority number, date | GB19930021366 | 15.10.1993 Original published format: GB 9321366 | [1995/16] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0649093 | Date: | 19.04.1995 | Language: | EN | [1995/16] | Type: | B1 Patent specification | No.: | EP0649093 | Date: | 04.03.1998 | Language: | EN | [1998/10] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 10.02.1995 | Classification | IPC: | G06F11/26 | [1995/16] | CPC: |
G06F11/27 (EP)
| Designated contracting states | DE, FR, GB, IT, NL [1995/16] | Title | German: | Prüfen logischer Gatter | [1995/16] | English: | Logic gate testing | [1995/16] | French: | Test de portes logiques | [1995/16] | Examination procedure | 10.03.1995 | Examination requested [1995/19] | 25.03.1997 | Despatch of communication of intention to grant (Approval: Yes) | 12.08.1997 | Communication of intention to grant the patent | 23.10.1997 | Fee for grant paid | 23.10.1997 | Fee for publishing/printing paid | Opposition(s) | 05.12.1998 | No opposition filed within time limit [1999/08] | Fees paid | Renewal fee | 21.10.1996 | Renewal fee patent year 03 | 29.10.1997 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]EP0073946 (SIEMENS AKTIENGESELLSCHAFT) [Y] 1-8 * abstract * * page 3, line 1 - line 5 * * page 4, line 29 - line 34 * * figure 1 *; | [DY]EP0509713 (BRITISH AEROSPACE PUBLIC LIMITED COMPANY) [DY] 1-8 * abstract * * page 4, line 31 - line 35 * * figure 7 *; | [YA]EP0491998 (IBM) [Y] 3 * abstract * * page 6, line 1 - line 6 * * page 11, line 50 - line 55 * * figures 2,14 * [A] 1 | [A] - M KANZAKI ET AL., "Programming for parallel pattern generators", PROCEEDINGS INTERNATIONAL TEST CONFERENCE 1991, pages 1061 - 1068 [A] 1,4 * page 1061, column R, line 19 - page 1063, column R, line 14 * * figures 1,2 * |