EP0632388 - Processor system particularly for image processing comprising a variable size memory bus [Right-click to bookmark this link] | |||
Former [1995/01] | Processor system particularly for image processing comprising a variable scize memory bus | ||
[1999/01] | Status | No opposition filed within time limit Status updated on 21.10.2000 Database last updated on 12.07.2024 | Most recent event Tooltip | 17.04.2015 | Change - lapse in a contracting state | published on 20.05.2015 [2015/21] | Applicant(s) | For all designated states STMicroelectronics S.A. 7, Avenue Galliéni 94250 Gentilly / FR | [1999/05] |
Former [1995/01] | For all designated states SGS-THOMSON MICROELECTRONICS S.A. 7, Avenue Galliéni F-94250 Gentilly / FR | Inventor(s) | 01 /
Artieri, Alain 7, Allée Eyminées F-38240 Meylan / FR | [1995/01] | Representative(s) | de Beaumont, Michel 1bis, rue Champollion 38000 Grenoble / FR | [N/P] |
Former [1995/01] | de Beaumont, Michel 1bis, rue Champollion F-38000 Grenoble / FR | Application number, filing date | 94410044.5 | 27.06.1994 | [1995/01] | Priority number, date | FR19930008218 | 30.06.1993 Original published format: FR 9308218 | [1995/01] | Filing language | FR | Procedural language | FR | Publication | Type: | A1 Application with search report | No.: | EP0632388 | Date: | 04.01.1995 | Language: | FR | [1995/01] | Type: | B1 Patent specification | No.: | EP0632388 | Date: | 22.12.1999 | Language: | FR | [1999/51] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 07.11.1994 | Classification | IPC: | G06F12/04, G06F13/40, H04N7/24 | [1995/01] | CPC: |
G06F12/04 (EP,US);
G06F13/4018 (EP,US);
H04N19/423 (EP,US);
H04N19/427 (EP,US);
H04N19/433 (EP,US);
H04N19/51 (EP,US);
H04N19/61 (EP,US)
(-)
| Designated contracting states | DE, FR, GB, IT [1995/01] | Title | German: | Prozessorsystem, insbesondere für Bildverarbeitung mit einem Speicherbus von variabler Grösse | [1995/01] | English: | Processor system particularly for image processing comprising a variable size memory bus | [1999/01] | French: | Système à processeur, notamment de traitement d'image comprenant un bus mémoire de taille variable | [1995/01] |
Former [1995/01] | Processor system particularly for image processing comprising a variable scize memory bus | Examination procedure | 14.06.1995 | Examination requested [1995/33] | 20.07.1998 | Despatch of a communication from the examining division (Time limit: M04) | 20.10.1998 | Reply to a communication from the examining division | 02.02.1999 | Despatch of communication of intention to grant (Approval: Yes) | 11.06.1999 | Communication of intention to grant the patent | 10.09.1999 | Fee for grant paid | 10.09.1999 | Fee for publishing/printing paid | Opposition(s) | 23.09.2000 | No opposition filed within time limit [2000/49] | Fees paid | Renewal fee | 10.06.1996 | Renewal fee patent year 03 | 10.06.1997 | Renewal fee patent year 04 | 15.06.1998 | Renewal fee patent year 05 | 14.06.1999 | Renewal fee patent year 06 |
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Former [2002/11] | DE | 23.03.2000 | Documents cited: | Search | [A]EP0189523 (TOSHIBA KK [JP]) [A] 1-5 * page 4, line 3 - page 5, line 27 *; | [A]JPH04114246 ; | [A]EP0522835 (SONY CORP [JP]) [A] 1 * abstract * * column 8, line 6 - line 53; figure 3 * | [A] - QUEROL, "MPEG/H261-Videodecoder mit wenigen Chips", ELEKTRONIK, MUNCHEN DE, (19921109), vol. 41, no. 23, pages 72 - 75, XP000320229 [A] 1 * the whole document * | [A] - WHITWORTH, "Designing flexibility into memory systems", MICROPROCESSORS AND MICROSYSTEMS, LONDON GB, (197912), vol. 3, no. 10, pages 435 - 441 [A] 1-5 * page 436, column L, line 6 - page 437, column R, line 7; figure 1 * | [A] - PATENT ABSTRACTS OF JAPAN, (19920807), vol. 16, no. 368, Database accession no. (P - 1398), & JP04114246 A 19920415 (HITACHI) [A] 1-4 * abstract * | [A] - BURSKY, "Image-processsing chip set handles full-motion video", ELECTRONIC DESIGN, HASBROUCK HEIGHTS, NEW JERSEY US, (19930503), vol. 41, no. 9, pages 117 - 120, XP000362680 [A] 1 * page 117; figure 1 * |