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Extract from the Register of European Patents

EP About this file: EP0712548

EP0712548 - ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS [Right-click to bookmark this link]
StatusNo opposition filed within time limit
Status updated on  06.02.2004
Database last updated on 23.04.2024
Most recent event   Tooltip28.12.2007Lapse of the patent in a contracting state
New state(s): IT		published on 30.01.2008  [2008/05]
Applicant(s)For all designated states
BTR, INC.
1 East 1st Street
Reno, NV 89501 / US
[1997/05]
Former [1996/21]For all designated states
ADVANTAGE LOGIC INC.
Suite 456, 20863 Stevens Creek Boulevard
Cupertino CA 95014 / US
Inventor(s)01 / TING, Benjamin, S.
21120 Sullivan Way
Saratoga, CA 95070 / US
[1996/21]
Representative(s)Wombwell, Francis, et al
Forresters
15, Hamilton Square
Birkenhead
Merseyside CH41 6BR / GB
[N/P]
Former [1996/21]Wombwell, Francis, et al
Potts, Kerr & Co. 15, Hamilton Square
Birkenhead Merseyside L41 6BR / GB
Application number, filing date94922455.424.06.1994
[1996/21]
WO1994US07187
Priority number, dateUS1993010119703.08.1993         Original published format: US 101197
[1996/21]
Filing languageEN
Procedural languageEN
PublicationType: A1 Application with search report
No.:WO9504404
Date:09.02.1995
Language:EN
[1995/07]
Type: A1 Application with search report 
No.:EP0712548
Date:22.05.1996
Language:EN
The application published by WIPO in one of the EPO official languages on 09.02.1995 takes the place of the publication of the European patent application.
[1996/21]
Type: B1 Patent specification 
No.:EP0712548
Date:02.04.2003
Language:EN
[2003/14]
Search report(s)International search report - published on:EP09.02.1995
ClassificationIPC:H03K19/177
[1996/21]
CPC:
H03K19/17704 (EP,US); H03K19/17728 (EP,US); H03K19/17736 (EP,US);
H03K19/1778 (EP,US); H03K19/17796 (EP,US)
Designated contracting statesAT,   BE,   CH,   DE,   DK,   ES,   FR,   GB,   GR,   IE,   IT,   LI,   LU,   MC,   NL,   PT,   SE [1996/21]
TitleGerman:ARCHITEKTUR-UND BESCHALTUNGSSCHEMA FÜR PROGRAMMIERBARE LOGISCHE SCHALTUNGEN[1996/21]
English:ARCHITECTURE AND INTERCONNECT SCHEME FOR PROGRAMMABLE LOGIC CIRCUITS[1996/21]
French:PLAN D'ARCHITECTURE ET D'INTERCONNEXION POUR CIRCUITS LOGIQUES PROGRAMMABLES[1996/21]
MiscellaneousEPB 1997/40: Teilanmeldung 97111287.5 eingereicht am 04/07/97
EPB 1997/40: Divisional application 97111287.5 filed on 04/07/97
EPB 1997/40: Demande divisionnaire 97111287.5 déposée le 04/07/97
Entry into regional phase01.03.1996National basic fee paid 
01.03.1996Designation fee(s) paid 
01.03.1996Examination fee paid 
Examination procedure23.02.1995Request for preliminary examination filed
International Preliminary Examining Authority: US
01.03.1996Examination requested  [1996/21]
01.10.1996Despatch of a communication from the examining division (Time limit: M04)
06.02.1997Reply to a communication from the examining division
19.02.1997Despatch of a communication from the examining division (Time limit: M04)
27.06.1997Reply to a communication from the examining division
13.08.1997Despatch of a communication from the examining division (Time limit: M04)
22.12.1997Reply to a communication from the examining division
20.05.1998Despatch of a communication from the examining division (Time limit: M04)
23.09.1998Reply to a communication from the examining division
20.05.1999Despatch of a communication from the examining division (Time limit: M06)
23.11.1999Reply to a communication from the examining division
05.04.2000Despatch of a communication from the examining division (Time limit: M06)
13.11.2000Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time
12.01.2001Reply to a communication from the examining division
01.10.2001Despatch of a communication from the examining division (Time limit: M04)
08.02.2002Reply to a communication from the examining division
19.06.2002Despatch of communication of intention to grant (Approval: Yes)
14.10.2002Communication of intention to grant the patent
17.12.2002Fee for grant paid
17.12.2002Fee for publishing/printing paid
Divisional application(s)EP97111287.5  / EP0806836
Opposition(s)05.01.2004No opposition filed within time limit [2004/13]
Request for further processing for:12.01.2001Request for further processing filed
12.01.2001Full payment received (date of receipt of payment)
Request granted
11.04.2001Decision despatched
Fees paidRenewal fee
13.05.1996Renewal fee patent year 03
13.05.1997Renewal fee patent year 04
23.06.1998Renewal fee patent year 05
04.06.1999Renewal fee patent year 06
05.06.2000Renewal fee patent year 07
06.06.2001Renewal fee patent year 08
24.06.2002Renewal fee patent year 09
Opt-out from the exclusive  Tooltip
competence of the Unified
Patent Court		 See the Register of the Unified Patent Court for opt-out data
Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court.
Lapses during opposition  TooltipAT02.04.2003
BE02.04.2003
CH02.04.2003
FR02.04.2003
IT02.04.2003
LI02.04.2003
NL02.04.2003
IE24.06.2003
LU24.06.2003
MC30.06.2003
DK02.07.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
[2008/05]
Former [2005/02]AT02.04.2003
BE02.04.2003
CH02.04.2003
FR02.04.2003
LI02.04.2003
NL02.04.2003
IE24.06.2003
LU24.06.2003
MC30.06.2003
DK02.07.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
Former [2004/39]AT02.04.2003
BE02.04.2003
CH02.04.2003
FR02.04.2003
LI02.04.2003
NL02.04.2003
IE24.06.2003
LU24.06.2003
DK02.07.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
Former [2004/35]AT02.04.2003
BE02.04.2003
CH02.04.2003
FR02.04.2003
LI02.04.2003
NL02.04.2003
IE24.06.2003
DK02.07.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
Former [2004/29]AT02.04.2003
BE02.04.2003
CH02.04.2003
LI02.04.2003
NL02.04.2003
IE24.06.2003
DK02.07.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
Former [2004/28]AT02.04.2003
BE02.04.2003
CH02.04.2003
LI02.04.2003
NL02.04.2003
DK02.07.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
Former [2004/23]AT02.04.2003
CH02.04.2003
LI02.04.2003
NL02.04.2003
DK02.07.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
Former [2004/05]AT02.04.2003
CH02.04.2003
LI02.04.2003
NL02.04.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
DE03.07.2003
ES30.10.2003
Former [2004/04]AT02.04.2003
CH02.04.2003
LI02.04.2003
NL02.04.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
ES30.10.2003
Former [2004/03]AT02.04.2003
CH02.04.2003
LI02.04.2003
NL02.04.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
Former [2004/02]CH02.04.2003
LI02.04.2003
NL02.04.2003
GR02.07.2003
PT02.07.2003
SE02.07.2003
Former [2004/01]CH02.04.2003
LI02.04.2003
NL02.04.2003
PT02.07.2003
SE02.07.2003
Former [2003/41]SE02.07.2003
Cited inInternational search[A]GB2180382  (PILKINGTON MICRO ELECTRONICS) [A] 1-3* figures 1-7 *;
 [A]EP0415542  (ADVANCED MICRO DEVICES INC [US]) [A] 1-3 * figures 4-15 *;
 [XA]WO9208286  (CONCURRENT LOGIC INC [US]) [X] 1-3 * page P9, line 15 - line 27; figure 3 * * page 8, line 9 - page 9, line 14; figures 5,6 * * page 10, line 15 - page 12, line 7; figures 7-9 * * page 6, line 5 - page 8, line 8; figure 3 * * page 10, line 29 - line 30 * * page 15, line 20 - line 35 * [A] 9,13,6,4,7
 [X]  - CLIFF ET AL, "a dual granularity and globally interconnected architecture for a programmable logic device", PROCEEDINGS OF THE IEEE 1993 CUSTOM INTEGRATED CIRCUITS CONFERENCE, NEW YORK, (199305), pages 7.3.1 - 7.3.5 [X] 1-3 * figures 1,2 *
 [X]  - BRITTON ET AL, "optimized reconfigurable cell array architecture for high-performance field programmable gate arrays", IEEE 1993 CUSTOM INTEGRATED CIRCUITS CONFERENCE, NEW YORK (US), (199305), pages 7.2.1 - 7.2.5 [X] 1-3 * figures 2-4 *
ExaminationUS4982114
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.