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EP0700003
European procedure
Extract from the Register of European Patents
EP About this file: EP0700003
| EP0700003 - Data processor with controlled burst memory accesses and method therefor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 30.08.2002 Database last updated on 02.08.2024 | Most recent event Tooltip | 30.08.2002 | No opposition filed within time limit | published on 16.10.2002 [2002/42] | Applicant(s) | For all designated states MOTOROLA, INC. 1303 East Algonquin Road Schaumburg, IL 60196 / US | [1996/10] | Inventor(s) | 01 /
Le, Chinh Hoang 2609 Greenland Lane Austin, Texas 78745 / US | 02 /
Eifert, James B. 800 Valley View Drive Austin, Texas 78733 / US | 03 /
Harwood, Wallace B., III 2806 Creeks Edge Pkwy Austin, Texas 78733 / US | [1996/10] | Representative(s) | Gibson, Sarah Jane, et al Motorola European Intellectual Property Operations Midpoint Alencon Link, Basingstoke Hampshire RG21 7PL / GB | [N/P] |
| Former [1996/10] | Spaulding, Sarah Jane, et al Motorola European Intellectual Property Midpoint Alencon Link Basingstoke, Hampshire RG21 1PL / GB | Application number, filing date | 95113370.1 | 25.08.1995 | [1996/10] | Priority number, date | US19940363423 | 21.12.1994 Original published format: US 363423 | US19940298868 | 31.08.1994 Original published format: US 298868 | [1996/10] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0700003 | Date: | 06.03.1996 | Language: | EN | [1996/10] | Type: | A3 Search report | No.: | EP0700003 | Date: | 01.05.1996 | [1996/18] | Type: | B1 Patent specification | No.: | EP0700003 | Date: | 24.10.2001 | Language: | EN | [2001/43] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 18.03.1996 | Classification | IPC: | G06F13/40, G06F13/42, G06F13/28, G06F12/08 | [1996/18] | CPC: |
G06F12/1441 (EP,US);
G06F13/16 (KR);
G06F13/28 (EP,US);
G06F13/4004 (EP,US);
G06F13/4018 (EP,US);
G06F13/4243 (EP,US)
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| Former IPC [1996/10] | G06F13/40, G06F13/42, G06F13/28 | Designated contracting states | DE, FR, GB, IE, IT, SE [1996/10] | Title | German: | Datenprozessor mit gesteuertem Stoss-Speicherzugriff und Vorrichtung dafür | [1996/10] | English: | Data processor with controlled burst memory accesses and method therefor | [1996/10] | French: | Processeur de données avec accès en mémoire en mode rafale contrôlé et méthode pour cela | [1996/10] | Examination procedure | 04.11.1996 | Examination requested [1997/01] | 18.02.1999 | Despatch of a communication from the examining division (Time limit: M04) | 25.06.1999 | Reply to a communication from the examining division | 30.07.1999 | Despatch of a communication from the examining division (Time limit: M04) | 07.12.1999 | Reply to a communication from the examining division | 12.09.2000 | Despatch of communication of intention to grant (Approval: Yes) | 28.12.2000 | Communication of intention to grant the patent | 09.04.2001 | Fee for grant paid | 09.04.2001 | Fee for publishing/printing paid | Opposition(s) | 25.07.2002 | No opposition filed within time limit [2002/42] | Fees paid | Renewal fee | 01.09.1997 | Renewal fee patent year 03 | 31.08.1998 | Renewal fee patent year 04 | 31.08.1999 | Renewal fee patent year 05 | 07.08.2000 | Renewal fee patent year 06 | 06.08.2001 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [XY]US5274780 (NAKAO YUICHI [JP]) [X] 1 * column 4, line 12 - column 5, line 38; figures 1-3 * [Y] 2,3; | [Y]FR2634919 (INTEL CORP [US]) [Y] 2,3 * page 11, line 18 - page 12, line 28 * * page 15, line 18 - page 17, line 15; figure 5 *; | [A]US5333294 (SCHNELL ARNOLD T [US]) [A] 1 * column 7, line 10 - column 8, line 69 *; | [Y]EP0523764 (PHILIPS NV [NL]) [Y] 4-7,9,10 * page 4, line 21 - page 5, line 49 *; | [Y]JPH04211880 ; | US5347643 [ ] (KONDO NOBUKAZU [JP], et al) [ ] * column 9, line 1 - column 10, line 3 *; | [YA]EP0358449 (COMPAQ COMPUTER CORP [US]) [Y] 8 * column 12, line 20 - column 13, line 53; figure 2 * * column 9, line 33 - column 12, line 24 * [A] 1,2; | [A]EP0535670 (BULL HN INFORMATION SYST [US]) [A] 1-3,8 * column 4, line 31 - column 6, line 19 *; | [A]US4910656 (SCALES III HUNTER L [US], et al) [A] 4-7,9,10,8 * column 2, line 22 - line 65 * * abstract *; | [A]US4912631 (LLOYD STACEY G [US]) [A] 8 * column 3, line 31 - column 4, line 46 *; | [A]GB2230117 (INTEL CORP [US]) [A] 8 * page 10, line 12 - page 16, line 16 * | [Y] - PATENT ABSTRACTS OF JAPAN, (19921125), vol. 16, no. 555, Database accession no. (P - 1454), & JP4211880 A 19920803 (HITACHI LTD.) [Y] 4-7,9,10 * abstract * | [Y] - "cache memory data bus to system bus interface", IBM TECHNICAL DISCLOSURE BULLETIN, ARMONK NY US, vol. 37, no. 02b, pages 451 - 453, XP000433908 [Y] 8 * the whole document * |