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EP0708482
European procedure
Extract from the Register of European Patents
EP About this file: EP0708482
| EP0708482 - BiCDMOS process technology. [Right-click to bookmark this link] | |||
| Former [1996/17] | BiCDMOS process technology and structures | ||
| [2003/22] | Status | No opposition filed within time limit Status updated on 28.10.2005 Database last updated on 03.06.2024 | Most recent event Tooltip | 17.02.2006 | Lapse of the patent in a contracting state | published on 05.04.2006 [2006/14] | Applicant(s) | For all designated states SILICONIX Incorporated 2201 Laurelwood Road Santa Clara, California 95054 / US | [N/P] |
| Former [1996/17] | For all designated states SILICONIX Incorporated 2201 Laurelwood Road Santa Clara California 95054 / US | Inventor(s) | 01 /
Williams, Richard K. 10292 Norwick Avenue Cupertino, CA 95014 / US | 02 /
Yilmaz, Hamza 18549 Paseo Pueblo Saratoga, CA 95070 / US | 03 /
Cornell, Michael E. 663 Regas Drive Campbell, CA 95008 / US | 04 /
Chen, Jun Wei 19725 Braemar Drive Saratoga, CA 95070 / US | [1996/17] | Representative(s) | Ebner von Eschenbach, Jennifer Ladas & Parry LLP Dachauerstrasse 37 80335 München / DE | [N/P] |
| Former [2004/06] | Ebner von Eschenbach, Jennifer Ladas & Parry, Dachauerstrasse 37 80335 München / DE | ||
| Former [1996/17] | Reinhard - Skuhra - Weise & Partner Postfach 44 01 51 D-80750 München / DE | Application number, filing date | 95116353.4 | 17.10.1995 | [1996/17] | Priority number, date | US19940323950 | 17.10.1994 Original published format: US 323950 | [1996/17] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0708482 | Date: | 24.04.1996 | Language: | EN | [1996/17] | Type: | A3 Search report | No.: | EP0708482 | Date: | 26.03.1997 | [1997/13] | Type: | B1 Patent specification | No.: | EP0708482 | Date: | 22.12.2004 | Language: | EN | [2004/52] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.02.1997 | Classification | IPC: | H01L21/8249, H01L27/06, H01L21/265 | [1997/09] | CPC: |
H01L29/7816 (EP,US);
H01L21/8249 (EP,US);
H01L27/0635 (EP,US);
H01L29/1004 (EP,US);
H01L29/66272 (EP,US);
H01L29/7322 (EP,US);
H01L29/7809 (EP,US);
H01L29/7835 (EP,US);
H01L29/0847 (EP,US);
H01L29/0878 (EP,US);
Y10S148/082 (EP,US);
Y10S148/126 (EP,US);
Y10S438/983 (EP,US)
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| Former IPC [1996/17] | H01L21/8249, H01L27/06 | Designated contracting states | DE, IT, NL [1996/17] | Title | German: | BiCDMOS-Herstellungstechnologie. | [2003/22] | English: | BiCDMOS process technology. | [2003/22] | French: | Technologie de fabrication BiCDMOS. | [2003/22] |
| Former [1996/17] | BiCDMOS-Herstellungstechnologie und ihre Strukturen | ||
| Former [1996/17] | BiCDMOS process technology and structures | ||
| Former [1996/17] | Technologie de fabrication BiCDMOS et ses structures | Examination procedure | 02.07.1997 | Examination requested [1997/36] | 10.08.1999 | Despatch of a communication from the examining division (Time limit: M06) | 07.02.2000 | Reply to a communication from the examining division | 04.05.2000 | Despatch of a communication from the examining division (Time limit: M06) | 27.10.2000 | Reply to a communication from the examining division | 20.08.2002 | Despatch of a communication from the examining division (Time limit: M06) | 18.02.2003 | Reply to a communication from the examining division | 24.09.2003 | Despatch of a communication from the examining division (Time limit: M06) | 29.03.2004 | Reply to a communication from the examining division | 14.06.2004 | Communication of intention to grant the patent | 19.10.2004 | Fee for grant paid | 19.10.2004 | Fee for publishing/printing paid | Opposition(s) | 23.09.2005 | No opposition filed within time limit [2005/50] | Fees paid | Renewal fee | 02.10.1997 | Renewal fee patent year 03 | 07.10.1998 | Renewal fee patent year 04 | 23.10.1999 | Renewal fee patent year 05 | 15.09.2000 | Renewal fee patent year 06 | 20.09.2001 | Renewal fee patent year 07 | 27.09.2002 | Renewal fee patent year 08 | 23.10.2003 | Renewal fee patent year 09 | 25.10.2004 | Renewal fee patent year 10 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | NL | 22.12.2004 | [2006/14] | Documents cited: | Search | [XA]EP0589675 (SILICONIX INC [US]) [X] 12,13 * page 7, line 7 - page 8, line 24; figures 11A-16A * * page 9, line 28 - line 40 * [A] 1,10,11; | [A]US4420872 (SOLO DE ZALDIVAR JOSE [CH]) [A] 1,2,6-8 * column 5, line 34 - column 6, line 59; figures 8-12 *; | [A]JPH01184956 ; | [A]JPS63160276 | [A] - PATENT ABSTRACTS OF JAPAN, (19891024), vol. 013, no. 470, Database accession no. (E - 835), & JP01184956 A 19890724 (HITACHI LTD) [A] 1,2,6,9,12 * abstract * | [A] - PATENT ABSTRACTS OF JAPAN, (19881109), vol. 012, no. 423, Database accession no. (E - 680), & JP63160276 A 19880704 (HITACHI LTD;OTHERS: 02) [A] 1,5,12 * abstract * | Examination | US4471373 | by applicant | US5426328 | US19940226419 | US19920948276 |