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EP0717415
European procedure
Extract from the Register of European Patents
EP About this file: EP0717415
| EP0717415 - Semiconductor memory device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 13.02.2004 Database last updated on 11.04.2026 | Most recent event Tooltip | 13.02.2004 | No opposition filed within time limit | published on 31.03.2004 [2004/14] | Applicant(s) | For all designated states Kabushiki Kaisha Toshiba 72, Horikawa-cho Saiwai-ku Kawasaki-shi Kanagawa-ken 210-8572 / JP | [N/P] |
| Former [2003/15] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210-8572 / JP | ||
| Former [1996/25] | For all designated states KABUSHIKI KAISHA TOSHIBA 72, Horikawa-cho, Saiwai-ku Kawasaki-shi, Kanagawa-ken 210 / JP | Inventor(s) | 01 /
Kaneko, Tetsuya, c/o Intellectual Property Div. Toshiba Corporation, 1-1-1, Shibaura Minato-ku, Tokyo / JP | [1996/25] | Representative(s) | Zangs, Rainer E., et al Hoffmann - Eitle ATTENTION : ADDRESS INACTIVE - USE ASS-NR - CDR / DE | [N/P] |
| Former [1996/25] | Zangs, Rainer E., Dipl.-Ing., et al Hoffmann, Eitle & Partner Arabellastrasse 4/VIII 81925 München / DE | Application number, filing date | 95118297.1 | 21.11.1995 | [1996/25] | Priority number, date | JP19940312991 | 16.12.1994 Original published format: JP 31299194 | [1996/25] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0717415 | Date: | 19.06.1996 | Language: | EN | [1996/25] | Type: | A3 Search report | No.: | EP0717415 | Date: | 25.08.1999 | [1999/34] | Type: | B1 Patent specification | No.: | EP0717415 | Date: | 09.04.2003 | Language: | EN | [2003/15] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 14.07.1999 | Classification | IPC: | G11C11/409, G11C7/06 | [1999/35] | CPC: |
G11C11/4087 (EP,US);
G11C11/40 (KR);
G11C11/4085 (EP,US);
G11C11/4091 (EP,US);
G11C5/145 (EP,US)
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| Former IPC [1996/25] | G11C11/409 | Designated contracting states | DE, FR, GB [1996/25] | Title | German: | Halbleiterspeicheranordnung | [1996/25] | English: | Semiconductor memory device | [1996/25] | French: | Dispositif de mémoire à semi-conducteurs | [1996/25] | Examination procedure | 21.09.1999 | Examination requested [1999/46] | 30.05.2001 | Despatch of a communication from the examining division (Time limit: M04) | 02.10.2001 | Reply to a communication from the examining division | 27.05.2002 | Despatch of communication of intention to grant (Approval: Yes) | 15.10.2002 | Communication of intention to grant the patent | 30.12.2002 | Fee for grant paid | 30.12.2002 | Fee for publishing/printing paid | Opposition(s) | 12.01.2004 | No opposition filed within time limit [2004/14] | Fees paid | Renewal fee | 10.11.1997 | Renewal fee patent year 03 | 10.11.1998 | Renewal fee patent year 04 | 12.11.1999 | Renewal fee patent year 05 | 13.11.2000 | Renewal fee patent year 06 | 14.11.2001 | Renewal fee patent year 07 | 13.11.2002 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X] US5267214 (FUJISHIMA KAZUYASU et al.) [X] 3-5 * column 12, line 248 - column 12, line 68 * * column 24, lines 10-20; figures 8,9 * | [X] JPH06203600 (SAMSUNG ELECTRONIC et al.) [X] 3,4 | [X] US5396465 (OH SEUNG-CHEOL et al.) * column 1, line 27 - column 2, line 44; figures 1,2 * | [A] US4710901 (KUMANOYA MASAKI et al.) [A] 1,2,9 * column 2, lines 20-40 * * column 5, line 30 - column 7, line 42; figures 1-3 * | [A] US5363333 (TSUJIMOTO AKIRA et al.) [A] 9,10 * column 7, line 53 - column 8, line 63; figure 17 * |