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Extract from the Register of European Patents

EP About this file: EP0676796

EP0676796 - Method for manufacturing a semiconductor substrate [Right-click to bookmark this link]
Former [1995/41]Semiconductor substrate and a method for manufacturing the same
[2000/46]
StatusNo opposition filed within time limit
Status updated on  29.08.2003
Database last updated on 24.04.2024
Most recent event   Tooltip29.08.2003No opposition filed within time limitpublished on 15.10.2003  [2003/42]
Applicant(s)For all designated states
CANON KABUSHIKI KAISHA
30-2, 3-chome, Shimomaruko, Ohta-ku
Tokyo / JP
[N/P]
Former [1995/41]For all designated states
CANON KABUSHIKI KAISHA
30-2, 3-chome, Shimomaruko, Ohta-ku
Tokyo / JP
Inventor(s)01 / Inoue, Shunsuke, c/o Canon K.K.
30-2, 3-chome Shimomaruko, Ohta-ku
Tokyo / JP
02 / Miyawaki, Mamoru, c/o Canon K.K.
30-2, 3-chome Shimomaruko, Ohta-ku
Tokyo / JP
03 / Fukumoto, Yoshihiko, c/o Canon K.K.
30-2, 3-chome Shimomaruko, Ohta-ku
Tokyo / JP
[1995/41]
Representative(s)Beresford, Keith Denis Lewis, et al
Beresford Crump LLP
16 High Holborn
London WC1V 6BX / GB
[N/P]
Former [1995/41]Beresford, Keith Denis Lewis, et al
BERESFORD & Co. 2-5 Warwick Court High Holborn
London WC1R 5DJ / GB
Application number, filing date95302253.004.04.1995
[1995/41]
Priority number, dateJP1994007039608.04.1994         Original published format: JP 7039694
[1995/41]
Filing languageEN
Procedural languageEN
PublicationType: A2 Application without search report 
No.:EP0676796
Date:11.10.1995
Language:EN
[1995/41]
Type: A3 Search report 
No.:EP0676796
Date:06.03.1996
[1996/10]
Type: B1 Patent specification 
No.:EP0676796
Date:23.10.2002
Language:EN
[2002/43]
Search report(s)(Supplementary) European search report - dispatched on:EP15.01.1996
ClassificationIPC:H01L21/20, H01L21/76
[1996/09]
CPC:
H01L21/76251 (EP,US); G02F1/136281 (EP,US); Y10S148/012 (EP)
Former IPC [1995/41]H01L21/20, H01L21/762
Designated contracting statesDE,   FR,   GB,   IT,   NL [1995/41]
TitleGerman:Verfahren zur Herstellung eines Halbleitersubstrates[2000/46]
English:Method for manufacturing a semiconductor substrate[2000/46]
French:Procédé de fabrication d'un substrat semi-conducteur[2000/46]
Former [1995/41]Halbleitersubstrat und Verfahren zur Herstellung
Former [1995/41]Semiconductor substrate and a method for manufacturing the same
Former [1995/41]Substrat semi-conducteur et procédé de fabrication
Examination procedure17.07.1996Examination requested  [1996/37]
20.08.1996Despatch of a communication from the examining division (Time limit: M06)
30.05.1997Reply to a communication from the examining division
26.01.1999Despatch of a communication from the examining division (Time limit: M06)
13.09.1999Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time
07.10.1999Reply to a communication from the examining division
27.04.2001Despatch of communication of intention to grant (Approval: No)
05.11.2001Despatch of communication of intention to grant (Approval: later approval)
15.04.2002Communication of intention to grant the patent
28.06.2002Fee for grant paid
28.06.2002Fee for publishing/printing paid
Opposition(s)24.07.2003No opposition filed within time limit [2003/42]
Request for further processing for:07.10.1999Request for further processing filed
07.10.1999Full payment received (date of receipt of payment)
Request granted
22.10.1999Decision despatched
30.05.1997Request for further processing filed
30.05.1997Full payment received (date of receipt of payment)
Request deemed not to be filed
24.07.1997Decision despatched
30.05.1996Request for further processing filed
30.05.1997Full payment received (date of receipt of payment)
Request deemed not to be filed
24.07.1997Decision despatched
Fees paidRenewal fee
23.04.1997Renewal fee patent year 03
23.04.1998Renewal fee patent year 04
21.04.1999Renewal fee patent year 05
20.04.2000Renewal fee patent year 06
26.04.2001Renewal fee patent year 07
23.04.2002Renewal fee patent year 08
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Documents cited:Search[A]US4939101  (BLACK ROBERT D [US], et al) [A] 1-8,11-14* column 6, line 60 - line 66; claims 1,5-7 *;
 [XY]US5213986  (PINKER RONALD D [US], et al) [X] 1,2,5,7,16-19 * column 3, line 3 - line 18; figures 1-3; claims 1-8 * [Y] 11-15;
 [YA]  - W.P. MASZARA, "EPI-LESS BOND-AND-ETCH-BACK SILICON -ON-INSULATOR BY MeV ION IMPLANTATION.", APPLIED PHYSICS LETTERS, NEW YORK US, (19910617), vol. 58, no. 24, doi:doi:10.1063/1.104784, pages 2779 - 2781, XP000233463 [Y] 11-15 * page 2779, column L, paragraph 3 - column R, paragraph 2 * [A] 9,10

DOI:   http://dx.doi.org/10.1063/1.104784
The EPO accepts no responsibility for the accuracy of data originating from other authorities; in particular, it does not guarantee that it is complete, up to date or fit for specific purposes.