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EP0698890
European procedure
Extract from the Register of European Patents
EP About this file: EP0698890
| EP0698890 - Testing an integrated circuit device [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 05.05.2001 Database last updated on 11.09.2024 | Most recent event Tooltip | 05.05.2001 | No opposition filed within time limit | published on 20.06.2001 [2001/25] | Applicant(s) | For all designated states STMicroelectronics Limited 1000 Aztec West, Almondsbury Bristol BS12 4SQ / GB | [N/P] |
| Former [1999/08] | For all designated states STMicroelectronics Limited 1000 Aztec West, Almondsbury Bristol BS12 4SQ / GB | ||
| Former [1996/09] | For all designated states SGS-THOMSON MICROELECTRONICS LTD. 1000 Aztec West, Almondsbury Bristol BS12 4SQ / GB | Inventor(s) | 01 /
McIntyre, Hugh 90 St. David's Crescent Newport, Gwent NP9 3AX / GB | [1996/09] | Representative(s) | Driver, Virginia Rozanne, et al Page White & Farrer Limited Bedford House 21A John Street London WC1N 2BF / GB | [N/P] |
| Former [1996/09] | Driver, Virginia Rozanne, et al Page White & Farrer 54 Doughty Street London WC1N 2LS / GB | Application number, filing date | 95305705.6 | 16.08.1995 | [1996/09] | Priority number, date | GB19940017268 | 26.08.1994 Original published format: GB 9417268 | [1996/09] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0698890 | Date: | 28.02.1996 | [1996/09] | Type: | B1 Patent specification | No.: | EP0698890 | Date: | 05.07.2000 | Language: | EN | [2000/27] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 06.12.1995 | Classification | IPC: | G11C29/00, G11C16/06, G06F11/20 | [1996/09] | CPC: |
G11C29/24 (EP,US);
G11C29/04 (EP,US);
G11C29/52 (EP,US)
| Designated contracting states | DE, FR, GB, IT [1996/09] | Title | German: | Prüfung einer integrierten Schaltungsanordnung | [1996/09] | English: | Testing an integrated circuit device | [1996/09] | French: | Test de dispositif à circuit intégré | [1996/09] | Examination procedure | 14.08.1996 | Examination requested [1996/41] | 01.04.1999 | Despatch of a communication from the examining division (Time limit: M04) | 14.06.1999 | Reply to a communication from the examining division | 20.08.1999 | Despatch of communication of intention to grant (Approval: Yes) | 13.01.2000 | Communication of intention to grant the patent | 06.03.2000 | Fee for grant paid | 06.03.2000 | Fee for publishing/printing paid | Opposition(s) | 06.04.2001 | No opposition filed within time limit [2001/25] | Fees paid | Renewal fee | 18.08.1997 | Renewal fee patent year 03 | 18.08.1998 | Renewal fee patent year 04 | 19.08.1999 | Renewal fee patent year 05 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]EP0420388 (SGS THOMSON MICROELECTRONICS [US]) [X] 1,2,4,5,15 * column 1, line 41 - column 2, line 49 * * column 3, line 48 - column 4, line 19; figure 2 *; | [X]EP0528744 (IBM [US]) [X] 1,5,6,15 * column 1, line 56 - column 2, line 26 * * column 3, line 1 - column 4, line 33; figure 1 *; | [X]US5233566 (IMAMIYA KENITI [JP], et al) [X] 1,5,6,15* the whole document * |