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EP0701219
European procedure
Extract from the Register of European Patents
EP About this file: EP0701219
| EP0701219 - Parallel processor apparatus [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 17.08.2001 Database last updated on 11.09.2024 | Most recent event Tooltip | 17.08.2001 | No opposition filed within time limit | published on 04.10.2001 [2001/40] | Applicant(s) | For all designated states Sony Corporation 7-35, Kitashinagawa 6-chome Shinagawa-ku Tokyo / JP | [N/P] |
| Former [2000/42] | For all designated states SONY CORPORATION 7-35, Kitashinagawa 6-chome Shinagawa-ku Tokyo / JP | ||
| Former [1996/11] | For all designated states SONY CORPORATION 6-7-35 Kitashinagawa Shinagawa-ku Tokyo 141 / JP | Inventor(s) | 01 /
Ohki, Mitsuharu Sony Corporation, 6-7-35 Kitashinagawa Shinagawa-ku, Tokyo 141 / JP | 02 /
Yamazaki, Takao Sony Corporation, 6-7-35 Kitashinagawa Shinagawa-ku, Tokyo 141 / JP | 03 /
Kurokawa, Masuyoshi Sony Corporation, 6-7-35 Kitashinagawa Shinagawa-ku, Tokyo 141 / JP | 04 /
Hashiguchi, Akihiko Sony Corporation, 6-7-35 Kitashinagawa Shinagawa-ku, Tokyo 141 / JP | [1996/11] | Representative(s) | Turner, James Arthur, et al D Young & Co LLP 120 Holborn London EC1N 2DY / GB | [N/P] |
| Former [1996/11] | Turner, James Arthur, et al D. Young & Co., 21 New Fetter Lane London EC4A 1DA / GB | Application number, filing date | 95306000.1 | 29.08.1995 | [1996/11] | Priority number, date | JP19940207805 | 31.08.1994 Original published format: JP 20780594 | [1996/11] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0701219 | Date: | 13.03.1996 | Language: | EN | [1996/11] | Type: | B1 Patent specification | No.: | EP0701219 | Date: | 18.10.2000 | Language: | EN | [2000/42] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.01.1996 | Classification | IPC: | G06F15/80, G06T1/20 | [1996/11] | CPC: |
G06F15/8015 (EP,US);
G06F9/38 (KR);
H04N5/14 (EP,US)
| Designated contracting states | DE, FR, GB [1996/11] | Title | German: | Parallelprozessorvorrichtung | [1996/11] | English: | Parallel processor apparatus | [1996/11] | French: | Dispositif à processeur parallèle | [1996/11] | Examination procedure | 19.07.1996 | Examination requested [1996/37] | 08.04.1999 | Despatch of a communication from the examining division (Time limit: M06) | 01.10.1999 | Reply to a communication from the examining division | 27.12.1999 | Despatch of communication of intention to grant (Approval: Yes) | 10.04.2000 | Communication of intention to grant the patent | 02.06.2000 | Fee for grant paid | 02.06.2000 | Fee for publishing/printing paid | Divisional application(s) | EP99203227.6 / EP0973100 | EP99203228.4 / EP0973101 | Opposition(s) | 19.07.2001 | No opposition filed within time limit [2001/40] | Fees paid | Renewal fee | 08.08.1997 | Renewal fee patent year 03 | 10.08.1998 | Renewal fee patent year 04 | 11.08.1999 | Renewal fee patent year 05 | 16.08.2000 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0210434 (IBM [US]) [A] 1-6 * column A * * page 12, line 1 - page 23, line 19 *; | [A]EP0422964 (TEXAS INSTRUMENTS INC [US]) [A] 1-8 * the whole document * | [XA] - TAMITANI I ET AL, "A real-time HDTV signal processor: HD-VSP", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, MARCH 1991, USA, ISSN 1051-8215, vol. 1, no. 1, doi:doi:10.1109/76.109144, pages 35 - 41, XP000208638 [X] 1-6 * paragraph [0IIA] * * paragraph [0IIB] * * paragraph [IIIA] * * paragraph [IIIC] * * figures 1-4 * [A] 7,8 DOI: http://dx.doi.org/10.1109/76.109144 | [DA] - CHILDERS J ET AL, "SVP: serial video processor", PROCEEDINGS OF THE IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE (CAT. NO.90CH2860-5), BOSTON, MA, USA, 13-16 MAY 1990, 1990, NEW YORK, NY, USA, IEEE, USA, pages 17.3/1 - 4 [DA] 1-8 * the whole document * | [A] - LIGON W B III ET AL, "Evaluating multigauge architectures for computer vision", JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, JUNE 1994, USA, ISSN 0743-7315, vol. 21, no. 3, doi:doi:10.1006/jpdc.1994.1063, pages 323 - 333, XP000450446 [A] 1 * page 325, column R, line 20 - line 49 * DOI: http://dx.doi.org/10.1006/jpdc.1994.1063 | by applicant | - CHILDERS, J. ET AL., "SVP: SERIAL VIDEO PROCESSOR/Proceedings of the IEEE", CUSTOM INTEGRATED CIRCUITS CONFERENCE, (1990), pages 17.3.1 - 17.3.4 |