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EP0709960
European procedure
Extract from the Register of European Patents
EP About this file: EP0709960
| EP0709960 - Variable delay circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 11.07.2003 Database last updated on 13.09.2024 | Most recent event Tooltip | 11.07.2003 | No opposition filed within time limit | published on 27.08.2003 [2003/35] | Applicant(s) | For all designated states Oki Electric Industry Co., Ltd. 7-12, Toranomon 1-chome, Minato-ku Tokyo 108 / JP | [1996/18] | Inventor(s) | 01 /
Yamada, Hiroyuki, c/o Oki Electric Ind Co, Ltd 7-12, Toranomon 1-chome, Minato-ku Tokyo 108 / JP | 02 /
Seki, Shouhei, c/o Oki Electric Ind Co, Ltd 7-12, Toranomon 1-chome, Minato-ku Tokyo 108 / JP | [1996/18] | Representative(s) | Boydell, John Christopher Stevens, Hewlett & Perkins Halton House 20/23 Holborn London EC1N 2JD / GB | [N/P] |
| Former [1996/18] | Boydell, John Christopher Stevens, Hewlett & Perkins 1 Serjeants' Inn Fleet Street London EC4Y 1LL / GB | Application number, filing date | 95307414.3 | 18.10.1995 | [1996/18] | Priority number, date | JP19940258185 | 24.10.1994 Original published format: JP 25818594 | [1996/18] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0709960 | Date: | 01.05.1996 | Language: | EN | [1996/18] | Type: | A3 Search report | No.: | EP0709960 | Date: | 19.03.1997 | [1997/12] | Type: | B1 Patent specification | No.: | EP0709960 | Date: | 04.09.2002 | Language: | EN | [2002/36] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 27.01.1997 | Classification | IPC: | H03K5/13, H03K5/151 | [1996/18] | CPC: |
H03K5/151 (EP,US);
H03K19/00 (KR);
H03K5/133 (EP,US)
| Designated contracting states | FR, GB, SE [1996/18] | Title | German: | Schaltung mit veränderlicher Verzögerung | [1996/18] | English: | Variable delay circuit | [1996/18] | French: | Circuit à retard variable | [1996/18] | Examination procedure | 05.09.1997 | Examination requested [1997/45] | 25.01.2002 | Despatch of communication of intention to grant (Approval: Yes) | 05.03.2002 | Communication of intention to grant the patent | 13.05.2002 | Fee for grant paid | 13.05.2002 | Fee for publishing/printing paid | Opposition(s) | 05.06.2003 | No opposition filed within time limit [2003/35] | Fees paid | Renewal fee | 22.09.1997 | Renewal fee patent year 03 | 01.10.1998 | Renewal fee patent year 04 | 02.10.1999 | Renewal fee patent year 05 | 18.10.2000 | Renewal fee patent year 06 | 04.10.2001 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0463854 (NEC CORP [JP]) [A] 1,8 * column 3, line 1 - column 5, line 6; figures 1-3 * | [DA] - K. TANAKA ET AL., "A GaAs DCFL Variable Delay Circuit for 2.5 GHz", PROCEEDINGS OF THE 1991 SPRING MEETING OF THE IEICE OF JAPAN, JP, (199103), page 5-106, XP002022105 [DA] 1,4,6,8 * the whole document * |