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EP0753215
European procedure
Extract from the Register of European Patents
EP About this file: EP0753215
| EP0753215 - ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS USING BIASED AND TERMINATED PNP TRANSISTOR CHAINS [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 08.06.2007 Database last updated on 14.09.2024 | Most recent event Tooltip | 28.11.2008 | Lapse of the patent in a contracting state | published on 31.12.2008 [2009/01] | Applicant(s) | For all designated states Intel Corporation 2200 Mission College Boulevard Santa Clara, CA 95054 / US | [N/P] |
| Former [1997/03] | For all designated states INTEL CORPORATION 2200 Mission College Boulevard Santa Clara, CA 95052 / US | Inventor(s) | 01 /
MALONEY, Timothy, J. 451 Matadero Avenue Palo Alto, CA 94306 / US | [1997/03] | Representative(s) | Wombwell, Francis Forresters 15, Hamilton Square Birkenhead Merseyside CH41 6BR / GB | [N/P] |
| Former [1997/03] | Wombwell, Francis Potts, Kerr & Co. 15, Hamilton Square Birkenhead Merseyside L41 6BR / GB | Application number, filing date | 95914895.8 | 27.03.1995 | [1997/03] | WO1995US03787 | Priority number, date | US19940218747 | 28.03.1994 Original published format: US 218747 | [1997/03] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO9526587 | Date: | 05.10.1995 | Language: | EN | [1995/42] | Type: | A1 Application with search report | No.: | EP0753215 | Date: | 15.01.1997 | Language: | EN | The application published by WIPO in one of the EPO official languages on 05.10.1995 takes the place of the publication of the European patent application. | [1997/03] | Type: | B1 Patent specification | No.: | EP0753215 | Date: | 02.08.2006 | Language: | EN | [2006/31] | Search report(s) | International search report - published on: | US | 05.10.1995 | (Supplementary) European search report - dispatched on: | EP | 14.10.1999 | Classification | IPC: | H02H9/00, H02H9/04, H01L27/02 | [1999/48] | CPC: |
H01L27/0259 (EP,KR,US);
H01L27/0251 (EP,KR,US);
H01L27/0255 (EP,KR,US);
H02H7/205 (KR)
|
| Former IPC [1997/03] | H02H9/00 | Designated contracting states | DE, FR [1997/03] | Title | German: | ELEKTROSTATISCHE ENTLADUNGSSCHUTZSCHALTUNGEN UNTER VERWENDUNG POLARISIERTER UND ABGESCHLOSSENER PNP TRANSISTORKETTEN | [1997/03] | English: | ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS USING BIASED AND TERMINATED PNP TRANSISTOR CHAINS | [1997/03] | French: | CIRCUITS ANTI-DECHARGES ELECTROSTATIQUES A CHAINES DE TRANSISTORS PNP POLARISES SE TERMINANT SUR UNE CHARGE | [1997/03] | Entry into regional phase | 28.09.1996 | National basic fee paid | 28.09.1996 | Search fee paid | 28.09.1996 | Designation fee(s) paid | 28.09.1996 | Examination fee paid | Examination procedure | 16.10.1995 | Request for preliminary examination filed International Preliminary Examining Authority: US | 28.09.1996 | Examination requested [1997/03] | 14.06.2004 | Despatch of a communication from the examining division (Time limit: M04) | 14.10.2004 | Reply to a communication from the examining division | 18.05.2005 | Despatch of a communication from the examining division (Time limit: M04) | 19.09.2005 | Reply to a communication from the examining division | 06.02.2006 | Communication of intention to grant the patent | 06.06.2006 | Fee for grant paid | 06.06.2006 | Fee for publishing/printing paid | Divisional application(s) | EP04024728.0 / EP1496591 | Opposition(s) | 03.05.2007 | No opposition filed within time limit [2007/28] | Fees paid | Renewal fee | 20.02.1997 | Renewal fee patent year 03 | 23.02.1998 | Renewal fee patent year 04 | 04.03.1999 | Renewal fee patent year 05 | 06.03.2000 | Renewal fee patent year 06 | 08.03.2001 | Renewal fee patent year 07 | 22.03.2002 | Renewal fee patent year 08 | 24.03.2003 | Renewal fee patent year 09 | 22.03.2004 | Renewal fee patent year 10 | 22.03.2005 | Renewal fee patent year 11 | 29.03.2006 | Renewal fee patent year 12 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | FR | 02.08.2006 | [2009/01] | Documents cited: | Search | [A]US5290724 (LEACH JERALD G [US]) [A] 1,11 * abstract * * column 10, line 54 - column 11, line 27 *; | [A]JPH0685176 ; | [A]US5124877 (GRAHAM ANDREW C [US]) [A] 1,11 * abstract *; | [A] - PATENT ABSTRACTS OF JAPAN, (19940624), vol. 018, no. 336, Database accession no. (E - 1568), & JP06085176 A 19940325 (KAWASAKI STEEL CORP) [A] 1,11 * abstract * | [A] - "ELECTROSTATIC DISCHARGE PROTECTION FOR MIXED VOLTAGE INTERFACE", IBM TECHNICAL DISCLOSURE BULLETIN, (19910901), vol. 34, no. 4A, ISSN 0018-8689, pages 222 - 223, XP000210887 [A] 1,11 * abstract * | [PA] - DABRAL S ET AL, "DESIGNING ON-CHIP POWER SUPPLY COUPLING DIODES FOR ESD PROTECTION AND NOISE IMMUNITY", JOURNAL OF ELECTROSTATICS, (19941001), vol. 33, no. 3, ISSN 0304-3886, pages 357 - 370, XP000477103 [PA] 1,11 * page 363, paragraph 4 - page 365, paragraph 5 * DOI: http://dx.doi.org/10.1016/0304-3886(94)90039-6 | International search | [Y]US3573550 (BAKER LOUIS P JR); | [YP]US5311391 (DUNGAN THOMAS [US], et al) |