-
EP0770292
European procedure
Extract from the Register of European Patents
EP About this file: EP0770292
| EP0770292 - TWO STAGE CLOCK DEJITTER CIRCUIT FOR REGENERATING AN E4 TELECOMMUNICATIONS SIGNAL FROM THE DATA COMPONENT OF AN STS-3C SIGNAL [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.08.2005 Database last updated on 14.09.2024 | Most recent event Tooltip | 16.03.2007 | Lapse of the patent in a contracting state | published on 18.04.2007 [2007/16] | Applicant(s) | For all designated states Transwitch Corporation 3 Enterprise Drive Shelton, CT 06484 / US | [2000/43] |
| Former [1997/18] | For all designated states TRANSWITCH CORPORATION 8 Progress Drive Shelton, CT 06484 / US | Inventor(s) | 01 /
UPP, Daniel, C. 15 Pepper Tree Hill Lane Southbury, CT 06488 / US | [1997/18] | Representative(s) | Gibson, Stewart Harry, et al Urquhart-Dykes & Lord LLP Churchill House Churchill Way Cardiff CF10 2HH / GB | [N/P] |
| Former [1997/18] | Gibson, Stewart Harry, et al URQUHART-DYKES & LORD, Three Trinity Court, 21-27 Newport Road Cardiff CF2 1AA / GB | Application number, filing date | 95925401.2 | 30.06.1995 | [1997/18] | WO1995US08260 | Priority number, date | US19940272259 | 08.07.1994 Original published format: US 272259 | [1997/18] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO9602095 | Date: | 25.01.1996 | Language: | EN | [1996/05] | Type: | A1 Application with search report | No.: | EP0770292 | Date: | 02.05.1997 | Language: | EN | The application published by WIPO in one of the EPO official languages on 25.01.1996 takes the place of the publication of the European patent application. | [1997/18] | Type: | B1 Patent specification | No.: | EP0770292 | Date: | 06.10.2004 | Language: | EN | [2004/41] | Search report(s) | International search report - published on: | US | 25.01.1996 | (Supplementary) European search report - dispatched on: | EP | 05.03.1999 | Classification | IPC: | H04J3/22, H04J3/07 | [1999/15] | CPC: |
G06F5/12 (EP,US);
H04J3/076 (EP,US);
G06F2205/061 (EP,US);
G06F2205/126 (EP,US)
|
| Former IPC [1997/18] | H04J3/22 | Designated contracting states | DE, FR, GB, SE [1997/18] | Title | German: | ZWEISTUFIGE TAKTFILTERSCHALTUNG ZUR REGENERIERUNG EINES E4 NACHRICHTENSIGNALS AUS DER DATENKOMPONENTE EINES STS-3C SIGNALS | [1997/18] | English: | TWO STAGE CLOCK DEJITTER CIRCUIT FOR REGENERATING AN E4 TELECOMMUNICATIONS SIGNAL FROM THE DATA COMPONENT OF AN STS-3C SIGNAL | [1997/18] | French: | CIRCUIT SUPPRESSEUR DE GIGUE D'HORLOGE A DEUX ETAGES, POUR RECREER UN SIGNAL DE TELECOMMUNICATIONS E4 A PARTIR DE LA COMPOSANTE DE DONNEES D'UN SIGNAL STS-3C | [1997/18] | Entry into regional phase | 22.01.1997 | National basic fee paid | 22.01.1997 | Search fee paid | 22.01.1997 | Designation fee(s) paid | 22.01.1997 | Examination fee paid | Examination procedure | 11.01.1996 | Request for preliminary examination filed International Preliminary Examining Authority: US | 22.01.1997 | Examination requested [1997/18] | 19.09.2002 | Despatch of a communication from the examining division (Time limit: M06) | 31.03.2003 | Reply to a communication from the examining division | 19.04.2004 | Communication of intention to grant the patent | 05.07.2004 | Fee for grant paid | 05.07.2004 | Fee for publishing/printing paid | Opposition(s) | 07.07.2005 | No opposition filed within time limit [2005/39] | Fees paid | Renewal fee | 19.06.1997 | Renewal fee patent year 03 | 09.06.1998 | Renewal fee patent year 04 | 22.06.1999 | Renewal fee patent year 05 | 06.06.2000 | Renewal fee patent year 06 | 11.06.2001 | Renewal fee patent year 07 | 07.06.2002 | Renewal fee patent year 08 | 28.05.2003 | Renewal fee patent year 09 | 13.05.2004 | Renewal fee patent year 10 |
| Opt-out from the exclusive Tooltip competence of the Unified Patent Court | See the Register of the Unified Patent Court for opt-out data | ||
| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | SE | 06.01.2005 | [2007/16] | Documents cited: | Search | [X]JPS5621440 ; | [X]US5245636 (SARI HIKMET [FR], et al) [X] 1-5 * column 1, line 36 - line 48 * * column 3, line 14 - line 47 * * column 6, line 62 - line 63 * * column 7, line 11 - line 25 * * column 7, line 51 - column 9, line 4 * * column 13, line 12 - line 15 *; | [A]WO9318595 (TRANSWITCH CORP [US]) [A] 1-12 * page 3, paragraph 3 - page 4, paragraph 2 * * page 11, paragraph 2 * * page 16, paragraph 1 ** page 19, paragraph 3 - page 20, paragraph 1; figure 2 *; | [X] - PATENT ABSTRACTS OF JAPAN, (19810516), vol. 005, no. 074, Database accession no. (E - 057), & JP56021440 A 19810227 (FUJITSU LTD) [X] 1-12 * abstract * | [X] - HAMLIN R W, "DESIGN AND PERFORMANCE VERIFICATION OF A SONET-TO-DS3 DESYNCHRONIZER", COUNTDOWN TO THE NEW MILENNIUM, PHOENIX, DEC. 2 - 5, 1991, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, (19911202), vol. 2, pages 761 - 764, XP000332777 [X] 1-12 * page 762, column L, paragraph 2 - column R, paragraph 1 * * figure 3 * DOI: http://dx.doi.org/10.1109/GLOCOM.1991.188485 | International search | [Y]US5142529 (PARRUCK BIDYUT [US], et al); | [Y]US5268936 (BERNARDY EDMOND [BE]); | [Y]US5311511 (REILLY BRIAN F [US], et al) |