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EP0741456
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EP About this file: EP0741456
| EP0741456 - Integrated circuit [Right-click to bookmark this link] | Status | The application has been refused Status updated on 25.07.1997 Database last updated on 14.09.2024 | Most recent event Tooltip | 25.07.1997 | Refusal of application | published on 10.09.1997 [1997/37] | Applicant(s) | For all designated states SIEMENS AKTIENGESELLSCHAFT Werner-von-Siemens-Str. 1 DE-80333 München / DE | [N/P] |
| Former [1996/45] | For all designated states SIEMENS AKTIENGESELLSCHAFT Wittelsbacherplatz 2 80333 München / DE | Inventor(s) | 01 /
Stecker, Johannes, Dr. rer. nat. Treitschkestr. 7 80992 München / DE | 02 /
Kristoffersson, Thomas Elsässer Strasse 25 81667 München / DE | 03 /
Chrysostomides, Ioannis Freischützstr. 25 81927 München / DE | [1996/45] | Application number, filing date | 96107366.5 | 04.05.1995 | [1996/45] | Filing language | DE | Procedural language | DE | Publication | Type: | A1 Application with search report | No.: | EP0741456 | Date: | 06.11.1996 | Language: | DE | [1996/45] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.08.1996 | Classification | IPC: | H03K19/00, H03K19/173, H03K19/003 | [1996/45] | CPC: |
G05F1/465 (EP);
H03K19/00 (KR);
H03K19/0027 (EP);
H03K19/018521 (EP);
H03K19/1732 (EP)
| Designated contracting states | AT, DE, FR, GB, IE, IT, NL [1996/45] | Title | German: | Integrierte Schaltung | [1996/45] | English: | Integrated circuit | [1996/45] | French: | Circuit intégré | [1996/45] | Examination procedure | 04.11.1996 | Request for accelerated examination filed | 18.11.1996 | Examination requested [1997/03] | 13.02.1997 | Despatch of a communication from the examining division (Time limit: M04) | 13.02.1997 | Decision about request for accelerated examination - accepted: Yes | 19.03.1997 | Reply to a communication from the examining division | 16.04.1997 | Despatch of communication that the application is refused, reason: substantive examination [1997/37] | 26.04.1997 | Application refused, date of legal effect [1997/37] | Parent application(s) Tooltip | EP95106753.7 / EP0743755 | Fees paid | Penalty fee | Additional fee for renewal fee | 31.05.1997 | 03 M06 Not yet paid |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [Y]US4952821 (KOKUBUN HITOSHI [JP]) [Y] 1,2,4 * column 1, line 10 - column 2, line 37; figure 1 *; | [A]EP0590326 (SIEMENS AG [DE]) [A] 1 * abstract *; | [DY] - MCCLINTOCK C ET AL, "A low power programmable logic device reconfigurable for 3.3 V or 5.0 V operation during and after fabrication", PROCEEDINGS OF THE IEEE 1994 CUSTOM INTEGRATED CIRCUITS CONFERENCE (CAT. NO.94CH3427-2), PROCEEDINGS OF IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE - CICC '94, SAN DIEGO, CA, USA, 1-4 MAY 1994, ISBN 0-7803-1886-2, 1994, NEW YORK, NY, USA, IEEE, USA, pages 177 - 180, XP002009428 [DY] 1,2,4 * the whole document * | [A] - G. W. DOERRE ET AL., "TTL Input Buffer with Variable Input Levels", IBM TECHNICAL DISCLOSURE BULLETIN, NEW YORK US, (198403), vol. 26, no. 10b, pages 5563 - 5564, XP002009669 |