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EP0800274
European procedure
Extract from the Register of European Patents
EP About this file: EP0800274
| EP0800274 - PLL circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 17.10.2003 Database last updated on 10.07.2024 | Most recent event Tooltip | 17.10.2003 | No opposition filed within time limit | published on 03.12.2003 [2003/49] | Applicant(s) | For all designated states MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100 / JP | [N/P] |
| Former [1997/41] | For all designated states MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100 / JP | Inventor(s) | 01 /
Yamaguchi, Atsuo, c/o Mitsubishi Denki K.K. 2-3, Marunouchi 2-chome, Chiyoda-ku Tokyo 100 / JP | [1997/41] | Representative(s) | Leson, Thomas Johannes Alois, et al TBK Bavariaring 4-6 80336 München / DE | [N/P] |
| Former [2002/38] | Leson, Thomas Johannes Alois, Dipl.-Ing., et al c/o TBK-Patent, P.O. Box 20 19 18 80019 München / DE | ||
| Former [1997/41] | Tiedtke, Harro, Dipl.-Ing. Patentanwaltsbüro Tiedtke-Bühling-Kinne & Partner Bavariaring 4 80336 München / DE | Application number, filing date | 96114005.0 | 02.09.1996 | [1997/41] | Priority number, date | JP19960083802 | 05.04.1996 Original published format: JP 8380296 | [1997/41] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0800274 | Date: | 08.10.1997 | Language: | EN | [1997/41] | Type: | A3 Search report | No.: | EP0800274 | Date: | 04.08.1999 | [1999/31] | Type: | B1 Patent specification | No.: | EP0800274 | Date: | 11.12.2002 | Language: | EN | [2002/50] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.06.1999 | Classification | IPC: | H03L7/00, H03L7/085, H03L7/089 | [1999/32] | CPC: |
H03L7/085 (EP,US);
H03L7/00 (KR);
H03L7/0898 (EP,US);
H03L7/099 (EP,US)
|
| Former IPC [1997/41] | H03L7/00 | Designated contracting states | DE, FR, GB [1997/41] | Title | German: | Phasenregelschaltung | [1997/41] | English: | PLL circuit | [1997/41] | French: | Circuit à boucle à verrouillage de phase | [1997/41] | Examination procedure | 06.09.1999 | Examination requested [1999/44] | 05.10.2001 | Despatch of a communication from the examining division (Time limit: M04) | 07.02.2002 | Reply to a communication from the examining division | 19.03.2002 | Despatch of communication of intention to grant (Approval: Yes) | 06.06.2002 | Communication of intention to grant the patent | 05.09.2002 | Fee for grant paid | 05.09.2002 | Fee for publishing/printing paid | Opposition(s) | 12.09.2003 | No opposition filed within time limit [2003/49] | Fees paid | Renewal fee | 29.09.1998 | Renewal fee patent year 03 | 27.09.1999 | Renewal fee patent year 04 | 28.09.2000 | Renewal fee patent year 05 | 28.09.2001 | Renewal fee patent year 06 | 30.09.2002 | Renewal fee patent year 07 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US5384502 (VOLK ANDREW M [US]) [X] 5 * column 8, line 11 - line 20; figure 4 *; | [A]EP0286329 (GIGABIT LOGIC INC [US]) [A] 1-10 * abstract *; | [A]WO9522206 (RAMBUS INC [US]) [A] 1-10 * abstract *; | [A]US5459755 (IGA TETSUYA [JP], et al) | [A] - SAM YINSHANG SUN, "AN ANALOG PLL-BASED CLOCK AND DATA RECOVERY CIRCUIT WITH HIGH INPUTJITTER TOLERANCE", IEEE JOURNAL OF SOLID-STATE CIRCUITS, (19890401), vol. 24, no. 2, pages 325 - 330, XP000069823 [A] * figure 4 * DOI: http://dx.doi.org/10.1109/4.18592 |