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EP0742517
European procedure
Extract from the Register of European Patents
EP About this file: EP0742517
| EP0742517 - A program translating apparatus and a processor which achieve high-speed execution of subroutine branch instructions [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 07.06.2002 Database last updated on 25.09.2024 | Most recent event Tooltip | 17.04.2015 | Change - lapse in a contracting state State(s) deleted from list of lapses: FR | published on 20.05.2015 [2015/21] | Applicant(s) | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi Osaka 571-8501 / JP | [2008/47] |
| Former [1996/46] | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Kadoma Kadoma-shi, Osaka-fu 571 / JP | Inventor(s) | 01 /
Takayama, Shuichi 1-22-6, Nakayamadai Takarazuka-shi, Hyogo 665 / JP | 02 /
Higaki, Nobuo Shaining-Sato 2H, 4-15-26, Komatsu Higashiyodogawa-ku, Osaka-shi, Osaka 533 / JP | 03 /
Tominaga, Nobuki Form-Fushimimomoyama 501, 215-1, Higashi-machi Fushimi-ku, Kyoto-shi, Kyoto 612 / JP | 04 /
Mijayi, Shinya 3-11-1, Jinguu, Nara-shi Nara 631 / JP | 05 /
Urushibara, Seiichi 5-15 Fukakusakawakubo-cho, Fukushimi-ku Kyoto-shi, Kyoto / JP | [1996/46] | Representative(s) | Crawford, Andrew Birkby, et al A.A. Thornton & Co. 235 High Holborn London WC1V 7LE / GB | [N/P] |
| Former [1996/46] | Crawford, Andrew Birkby, et al A.A. THORNTON & CO. Northumberland House 303-306 High Holborn London WC1V 7LE / GB | Application number, filing date | 96301214.1 | 23.02.1996 | [1996/46] | Priority number, date | JP19950111701 | 10.05.1995 Original published format: JP 11170195 | [1996/46] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0742517 | Date: | 13.11.1996 | Language: | EN | [1996/46] | Type: | A3 Search report | No.: | EP0742517 | Date: | 28.05.1997 | [1997/22] | Type: | B1 Patent specification | No.: | EP0742517 | Date: | 01.08.2001 | Language: | EN | [2001/31] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 15.04.1997 | Classification | IPC: | G06F9/45, G06F9/445, G06F9/32 | [1997/21] | CPC: |
G06F8/447 (EP,US);
G06F8/40 (KR);
G06F8/4451 (EP,US);
G06F8/54 (EP,US)
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| Former IPC [1996/46] | G06F9/45 | Designated contracting states | DE, FR, GB, NL [1996/46] | Title | German: | Programmübersetzungsgerät und Prozessor, die eine schnelle Ausführung von Unterprogrammsprungbefehlen erreichen | [1996/46] | English: | A program translating apparatus and a processor which achieve high-speed execution of subroutine branch instructions | [1996/46] | French: | Appareil de traduction de programmes et processeur achevant l'exécution à haute vitesse d'instructions de branchement à des sous-programmes | [1996/46] | Examination procedure | 09.10.1997 | Examination requested [1997/49] | 31.10.2000 | Despatch of communication of intention to grant (Approval: Yes) | 07.02.2001 | Communication of intention to grant the patent | 04.05.2001 | Fee for grant paid | 04.05.2001 | Fee for publishing/printing paid | Opposition(s) | 03.05.2002 | No opposition filed within time limit [2002/30] | Fees paid | Renewal fee | 11.02.1998 | Renewal fee patent year 03 | 10.02.1999 | Renewal fee patent year 04 | 11.02.2000 | Renewal fee patent year 05 | 15.02.2001 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | deleted | [2015/21] |
| Former [2002/18] | FR | 28.12.2001 | Documents cited: | Search | [A]US5375242 (KUMAR RAJIV [US], et al) [A] 1,4,7 * the whole document * | [Y] - MCGEADY S, "Inside Intel's i960CA superscalar processor", MICROPROCESSORS AND MICROSYSTEMS, JULY-AUG. 1990, UK, ISSN 0141-9331, vol. 14, no. 6, pages 385 - 396, XP000151094 [Y] 1-9 * page 387, column R, line 12 - line 20; table 3 * * page 388, column L, line 48 - column R, line 11 * * page 388, column R, line 28 - page 389, column L, line 9 * * page 389, column L, line 18 - line 29 * * page 389, column R, line 38 - line 59; figures 4,5 * DOI: http://dx.doi.org/10.1016/0141-9331(90)90111-8 | [Y] - GONZALEZ A M, "A SURVEY OF BRANCH TECHNIQUES IN PIPELINED PROCESSORS", MICROPROCESSING AND MICROPROGRAMMING, (19931001), vol. 36, no. 5, pages 243 - 257, XP000397907 [Y] 1-9 * page 246, column R, line 1 - page 248, column L, line 2; figure 2B * DOI: http://dx.doi.org/10.1016/0165-6074(93)90263-K |