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EP0734124
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EP About this file: EP0734124
| EP0734124 - Filter network for phase-locked loop circuit [Right-click to bookmark this link] | Status | The application has been withdrawn Status updated on 16.01.1998 Database last updated on 12.08.2024 | Most recent event Tooltip | 16.01.1998 | Withdrawal of application | published on 04.03.1998 [1998/10] | Applicant(s) | For all designated states International Business Machines Corporation New Orchard Road Armonk, NY 10504 / US | [N/P] |
| Former [1996/39] | For all designated states International Business Machines Corporation Old Orchard Road Armonk, N.Y. 10504 / US | Inventor(s) | 01 /
Gersback, John Edwin 500 S. Willard Street Burlington, VT 05401 / US | 02 /
Williams, Todd P.O. Box 60471 Sunnyvale, CA 94088-0471 / US | [1996/39] | Representative(s) | de Pena, Alain, et al Compagnie IBM France Département de la Propriété Intellectuelle 06610 La Gaude / FR | [N/P] |
| Former [1997/12] | de Pena, Alain, et al Compagnie IBM France Département de Propriété Intellectuelle 06610 La Gaude / FR | ||
| Former [1996/39] | Lattard, Nicole Compagnie IBM France Département de Propriété Intellectuelle 06610 La Gaude / FR | Application number, filing date | 96480025.4 | 05.03.1996 | [1996/39] | Priority number, date | US19950407346 | 20.03.1995 Original published format: US 407346 | [1996/39] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0734124 | Date: | 25.09.1996 | Language: | EN | [1996/39] | Type: | A3 Search report | No.: | EP0734124 | Date: | 12.03.1997 | [1997/11] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 23.01.1997 | Classification | IPC: | H03L7/093 | [1996/39] | CPC: |
H03L7/093 (EP,US);
H03L7/099 (EP,US);
H03L7/1075 (EP,US);
H03L2207/06 (EP,US);
H03L7/10 (EP,US)
| Designated contracting states | DE, FR, GB [1996/39] | Title | German: | Filterschaltung für einen Phasenregelkreis | [1996/39] | English: | Filter network for phase-locked loop circuit | [1996/39] | French: | Circuit de filtrage pour boucle à synchronisation de phase | [1996/39] | Examination procedure | 20.01.1997 | Examination requested [1997/13] | 23.12.1997 | Application withdrawn by applicant [1998/10] |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0330984 (LICENTIA GMBH [DE]) [A] 1-3,8 * page 3, line 12 - page 4, line 32; figures 3,4 *; | [A]US5382922 (GERSBACH JOHN E [US], et al) [A] 1,2,7-9 * column 4, line 34 - column 6, line 35; figures 1,4 *; | [A]US4904957 (COQUEREL PATRICK [FR]) [A] 1,8 * column 3, line 32 - column 5, line 16; figures 2,3 *; | [A] - M. J. UNDERHILL ET AL., "Split-Loop Method For Wide Range Frequency Synthesiser With Good Dynamic Performance", ELECTRONICS LETTERS, STEVENAGE GB, (197606), vol. 15, no. 13, pages 391 - 393, XP002022974 [A] 1-4,8 * the whole document * |