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EP0979463
European procedure
Extract from the Register of European Patents
EP About this file: EP0979463
| EP0979463 - SYSTEM AND METHOD FOR GENERATING FRACTIONAL LENGTH DELAY LINES IN A DIGITAL SIGNAL PROCESSING SYSTEM [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 14.11.2003 Database last updated on 03.06.2024 | Most recent event Tooltip | 14.11.2003 | No opposition filed within time limit | published on 02.01.2004 [2004/01] | Applicant(s) | For all designated states THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY 900 Welch Road, Suite 350 Stanford, CA 94304 / US | [N/P] |
| Former [2000/07] | For all designated states THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY 900 Welch Road, Suite 350 Stanford, CA 94304 / US | Inventor(s) | 01 /
VAN DUYNE, Scott A. 68-F Escondido Village Stanford, CA 94305 / US | 02 /
JAFFE, David A. 739 Hilldale Avenue Berkeley, CA 94708 / US | 03 /
SCANDALIS, Gregory P. 286 Carmelita Mountain View, CA 94040 / US | 04 /
STILSON, Timothy S Apartment 303, 2685 California Street Mountain View, CA 94040 / US | [2000/07] | Representative(s) | Cross, Rupert Edward Blount, et al Boult Wade Tennant Verulam Gardens 70 Gray's Inn Road London WC1X 8BT / GB | [N/P] |
| Former [2000/07] | Cross, Rupert Edward Blount, et al BOULT WADE TENNANT, 27 Furnival Street London EC4A 1PQ / GB | Application number, filing date | 97918513.9 | 03.04.1997 | [2000/07] | WO1997US05610 | Priority number, date | US19960647296 | 09.05.1996 Original published format: US 647296 | [2000/07] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | WO9742583 | Date: | 13.11.1997 | Language: | EN | [1997/49] | Type: | A1 Application with search report | No.: | EP0979463 | Date: | 16.02.2000 | Language: | EN | The application published by WIPO in one of the EPO official languages on 13.11.1997 takes the place of the publication of the European patent application. | [2000/07] | Type: | B1 Patent specification | No.: | EP0979463 | Date: | 02.01.2003 | Language: | EN | [2003/01] | Search report(s) | International search report - published on: | US | 13.11.1997 | (Supplementary) European search report - dispatched on: | EP | 29.02.2000 | Classification | IPC: | G06F17/17, G10H1/00, G10H1/12 | [2000/15] | CPC: |
G06F17/17 (EP,US);
G10H2250/035 (EP,US);
G10H2250/046 (EP,US);
G10H2250/101 (EP,US)
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| Former IPC [2000/07] | G06F17/17 | Designated contracting states | DE, GB [2000/07] | Title | German: | SYSTEM UND VERFAHREN ZUM GENERIEREN FRAKTIONELLER LÄNGENAUFSCHUBLINIEN IN EINEM DIGITALEN SIGNALVERARBEITUNGSSYSTEM | [2000/07] | English: | SYSTEM AND METHOD FOR GENERATING FRACTIONAL LENGTH DELAY LINES IN A DIGITAL SIGNAL PROCESSING SYSTEM | [2000/07] | French: | SYSTEME ET PROCEDE DE PRODUCTION DE LIGNES FRACTIONNELLES A RETARD EN DISTANCE, DANS UN SYSTEME DE TRAITEMENT DE SIGNAUX NUMERIQUES | [2000/07] | Entry into regional phase | 07.12.1998 | National basic fee paid | 07.12.1998 | Search fee paid | 07.12.1998 | Designation fee(s) paid | 07.12.1998 | Examination fee paid | Examination procedure | 15.10.1997 | Request for preliminary examination filed International Preliminary Examining Authority: US | 07.12.1998 | Examination requested [2000/07] | 11.05.2001 | Despatch of a communication from the examining division (Time limit: M06) | 15.10.2001 | Reply to a communication from the examining division | 25.04.2002 | Despatch of communication of intention to grant (Approval: Yes) | 23.07.2002 | Communication of intention to grant the patent | 17.10.2002 | Fee for grant paid | 17.10.2002 | Fee for publishing/printing paid | Opposition(s) | 03.10.2003 | No opposition filed within time limit [2004/01] | Fees paid | Renewal fee | 19.03.1999 | Renewal fee patent year 03 | 06.03.2000 | Renewal fee patent year 04 | 21.03.2001 | Renewal fee patent year 05 | 22.04.2002 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]US5256830 (TAKEUCHI CHIFUMI [JP], et al) [A] 1,5,9 * column 8, line 43 - column 9, line 33; figure 3 *; | [A]US5338892 (SEKINE SATOSHI [JP], et al) [A] 1,5,9 * column 5, line 18 - column 6, line 42; figure 3 * | International search | [X]US4726067 (ALONSO SYDNEY A [US]); | [A]US5500486 (SMITH III JULIUS O [US]); | [AP]US5583309 (FUJITA YOSHIO [JP]) |