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EP0863471
European procedure
Extract from the Register of European Patents
EP About this file: EP0863471
| EP0863471 - Semiconductor integrated circuit with two supply voltages [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 11.07.2003 Database last updated on 12.07.2024 | Most recent event Tooltip | 17.10.2008 | Change - applicant | published on 19.11.2008 [2008/47] | Applicant(s) | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi Osaka 571-8501 / JP | [2008/47] |
| Former [2002/36] | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi, Osaka 571-0050 / JP | ||
| Former [1998/37] | For all designated states MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 1006, Oaza Kadoma Kadoma-shi, Osaka 571 / JP | Inventor(s) | 01 /
Ohara, Kazutake 4-13-317, Shimohozumi Ibaraki-shi, Osaka 567 / JP | [1998/37] | Representative(s) | Grünecker Patent- und Rechtsanwälte PartG mbB Leopoldstraße 4 80802 München / DE | [N/P] |
| Former [1998/37] | Grünecker, Kinkeldey, Stockmair & Schwanhäusser Anwaltssozietät Maximilianstrasse 58 80538 München / DE | Application number, filing date | 98107368.7 | 18.01.1995 | [1998/37] | Priority number, date | JP19940004024 | 19.01.1994 Original published format: JP 402494 | [1998/37] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0863471 | Date: | 09.09.1998 | Language: | EN | [1998/37] | Type: | A3 Search report | No.: | EP0863471 | Date: | 17.02.1999 | [1999/07] | Type: | B1 Patent specification | No.: | EP0863471 | Date: | 04.09.2002 | Language: | EN | [2002/36] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 05.01.1999 | Classification | IPC: | G06F17/50, H03K19/00 | [1999/06] | CPC: |
G06F30/327 (EP,US);
H01L21/82 (KR)
|
| Former IPC [1998/37] | G06F17/50 | Designated contracting states | DE, FR, GB [1998/37] | Title | German: | Intergrierte Halbleiterschaltung mit zwei Versorgungsspannungen | [1998/37] | English: | Semiconductor integrated circuit with two supply voltages | [1998/37] | French: | Circuit intégré à semi-conducteur avec deux tensions d'alimentation | [1998/37] | Examination procedure | 22.04.1998 | Examination requested [1998/37] | 09.12.1999 | Despatch of a communication from the examining division (Time limit: M04) | 19.04.2000 | Reply to a communication from the examining division | 16.11.2001 | Despatch of communication of intention to grant (Approval: Yes) | 05.03.2002 | Communication of intention to grant the patent | 03.06.2002 | Fee for grant paid | 03.06.2002 | Fee for publishing/printing paid | Parent application(s) Tooltip | EP95100625.3 / EP0664517 | Opposition(s) | 05.06.2003 | No opposition filed within time limit [2003/35] | Fees paid | Renewal fee | 22.04.1998 | Renewal fee patent year 03 | 22.04.1998 | Renewal fee patent year 04 | 28.01.1999 | Renewal fee patent year 05 | 27.01.2000 | Renewal fee patent year 06 | 30.01.2001 | Renewal fee patent year 07 | 30.01.2002 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DXY]JPH05299624 ; | [DYA]JPH0567963 ; | [A]JPH04253366 (TOSHIBA CORP) [A] 1,6-13; | US5352942 [ ] (TANAKA YASUNORI [JP], et al) [ ] * column 1, line 1 - line 68 * * column 5, line 8 - column 6, line 65 * * column 10, line 25 - column 11, line 20 * * column 14, line 40 - column 17, line 11; figures 2,3,7,13-15 *; | [A]US5119314 (HOTTA TAKASHI [JP], et al) [A] 1 * column 2, line 35 - column 3, line 2 * * column 7, line 22 - column 7, line 62; figure 15 *; | [DXY] - PATENT ABSTRACTS OF JAPAN, (19940216), vol. 018, no. 095, Database accession no. (E - 1509), & JP05299624 A 19931112 (MITSUBISHI ELECTRIC CORP) [DX] 1,2,19,20 * figures 1,2 * [Y] 6 | [DYA] - PATENT ABSTRACTS OF JAPAN, (19930720), vol. 017, no. 386, Database accession no. (E - 1401), & JP05067963 A 19930319 (HITACHI LTD; OTHERS: 01) [DY] 6 * abstract * [A] 7-13 | [A] - KOJIMA H ET AL, "Half-swing clocking scheme for 75% power saving in clocking circuitry", 1994 SYMPOSIUM ON VLSI CIRCUITS. DIGEST OF TECHNICAL PAPERS (CAT. NO.94CH3434-8), PROCEEDINGS OF 1994 IEEE SYMPOSIUM ON VLSI CIRCUITS, HONOLULU, HI, USA, 9-11 JUNE 1994, ISBN 0-7803-1918-4, 1994, New York, NY, USA, IEEE, USA, pages 23 - 24, XP002087571 [A] 9 | [A] - E. J. MCCLUSKEY, Logic Design Principles, ENGLEWOOD CLIFFS, NEW JERSEY, PRENTICE-HALL, (1986), 539784, XP002087572 [A] 14 * page 439 - page 440 * |