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EP0911733
European procedure
Extract from the Register of European Patents
EP About this file: EP0911733
| EP0911733 - Circuit for interrupt signal generation in a microprocessor [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 01.10.2004 Database last updated on 19.10.2024 | Most recent event Tooltip | 01.10.2004 | No opposition filed within time limit | published on 17.11.2004 [2004/47] | Applicant(s) | For all designated states Infineon Technologies AG St.-Martin-Strasse 53 81669 München / DE | [2001/26] |
| Former [1999/17] | For all designated states SIEMENS AKTIENGESELLSCHAFT Wittelsbacherplatz 2 80333 München / DE | Inventor(s) | 01 /
Barrenscheen, Jens Franziskanerstrasse 16 81669 München / DE | [1999/17] | Representative(s) | Jannig, Peter Jannig & Repkow Patentanwälte PartG mbB Klausenberg 20 86199 Augsburg / DE | [N/P] |
| Former [2001/26] | Jannig, Peter, Dipl.-Ing. Jannig & Repkow, Patentanwälte, Klausenberg 20 86199 Augsburg / DE | Application number, filing date | 98115551.8 | 18.08.1998 | [1999/17] | Priority number, date | DE19971039530 | 09.09.1997 Original published format: DE 19739530 | [1999/17] | Filing language | DE | Procedural language | DE | Publication | Type: | A2 Application without search report | No.: | EP0911733 | Date: | 28.04.1999 | Language: | DE | [1999/17] | Type: | A3 Search report | No.: | EP0911733 | Date: | 30.01.2002 | [2002/05] | Type: | B1 Patent specification | No.: | EP0911733 | Date: | 26.11.2003 | Language: | DE | [2003/48] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 13.12.2001 | Classification | IPC: | G06F11/00, G06F13/24 | [2002/04] | CPC: |
G06F13/24 (EP,US);
G06F11/00 (KR)
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| Former IPC [1999/17] | G06F11/00 | Designated contracting states | DE, FR, GB, IT [2002/42] |
| Former [1999/17] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Schaltungsanordnung zur Erzeugung eines Interruptsignals für einen Mikroprozessor | [1999/17] | English: | Circuit for interrupt signal generation in a microprocessor | [1999/17] | French: | Circuit de génération de signal d' interruption pour un microprocesseur | [1999/17] | Examination procedure | 27.07.2002 | Examination requested [2002/40] | 20.05.2003 | Communication of intention to grant the patent | 24.09.2003 | Fee for grant paid | 24.09.2003 | Fee for publishing/printing paid | Opposition(s) | 27.08.2004 | No opposition filed within time limit [2004/47] | Fees paid | Renewal fee | 17.08.2000 | Renewal fee patent year 03 | 31.08.2001 | Renewal fee patent year 04 | 24.08.2002 | Renewal fee patent year 05 | 20.08.2003 | Renewal fee patent year 06 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [DA]DD940231 (HEINRICH MUNZ) [DA] 1-6 * figure 1; claims 1-6 *; | [A]JPH0844572 ; | [DA]DE2654247 (SIEMENS AG) [DA] 1-6 * the whole document *; | [A]US5638016 (EITRHEIM JOHN K [US]) [A] 1 * column 2, line 54 - line 64; figure 1 *; | [A] - PATENT ABSTRACTS OF JAPAN, (19960628), vol. 1996, no. 06, & JP08044572 A 19960216 (NEC CORP) [A] 1-6 * abstract * | [A] - ANONYMOUS, "Sharing Method of Edge-Mode Interrupt Signal", IBM TECHNICAL DISCLOSURE BULLETIN, New York, US, (19951201), vol. 38, no. 12, pages 185 - 186, XP002167859 [A] 1-6 * the whole document * |