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EP0871292
European procedure
Extract from the Register of European Patents
EP About this file: EP0871292
| EP0871292 - In-system programmable interconnect circuit [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 04.10.2002 Database last updated on 03.10.2024 | Most recent event Tooltip | 04.10.2002 | No opposition filed within time limit | published on 20.11.2002 [2002/47] | Applicant(s) | For all designated states LATTICE SEMICONDUCTOR CORPORATION 5555 N.E. Moore Court Hillsboro, Oregon 97124 / US | [N/P] |
| Former [1998/42] | For all designated states LATTICE SEMICONDUCTOR CORPORATION 5555 N.E. Moore Court Hillsboro, Oregon 97124 / US | Inventor(s) | 01 /
Kopec, Stanley J., Jr. 12430 Northwest Woodland Court Portland, OR 97229 / US | 02 /
Wang, Cheng-Yuan Michael 1566 Deluca Drive San Jose, CA 95134 / US | 03 /
Farmer, Jerome Connelly 350 Elan Village No. 222 San Jose, CA 95134 / US | 04 /
Tsui, Cyrus Y. 5555 NE Moore Court Hillsboro, Oregon 97124 / US | [1998/42] | Representative(s) | Atkinson, Ralph, et al Atkinson & Company Intellectual Property Limited 7 Moorgate Road Rotherham South Yorkshire S60 2BF / GB | [N/P] |
| Former [1998/42] | Atkinson, Ralph, et al Atkinson & Co., PO Box 1205 Sheffield S9 3UR / GB | Application number, filing date | 98302420.9 | 30.03.1998 | [1998/42] | Priority number, date | US19970838487 | 07.04.1997 Original published format: US 838487 | [1998/42] | Filing language | EN | Procedural language | EN | Publication | Type: | A1 Application with search report | No.: | EP0871292 | Date: | 14.10.1998 | Language: | EN | [1998/42] | Type: | B1 Patent specification | No.: | EP0871292 | Date: | 28.11.2001 | Language: | EN | [2001/48] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 31.07.1998 | Classification | IPC: | H03K19/177 | [1998/42] | CPC: |
H03K19/17736 (EP,US);
H03K19/1774 (EP,US);
H03K19/17744 (EP,US)
| Designated contracting states | DE, GB [1999/25] |
| Former [1998/42] | AT, BE, CH, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Im System programmierbarer Verbindungsschaltkreis | [1998/42] | English: | In-system programmable interconnect circuit | [1998/42] | French: | Réseau d'interconnexion programmable après installation | [1998/42] | Examination procedure | 09.04.1999 | Examination requested [1999/23] | 22.09.1999 | Despatch of a communication from the examining division (Time limit: M06) | 04.03.2000 | Reply to a communication from the examining division | 15.01.2001 | Despatch of communication of intention to grant (Approval: Yes) | 18.05.2001 | Communication of intention to grant the patent | 09.08.2001 | Fee for grant paid | 09.08.2001 | Fee for publishing/printing paid | Opposition(s) | 29.08.2002 | No opposition filed within time limit [2002/47] | Fees paid | Renewal fee | 06.03.2000 | Renewal fee patent year 03 | 08.03.2001 | Renewal fee patent year 04 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [X]US5237218 (JOSEPHSON GREGG R [US], et al) [X] 1-7,15,16 * column 2, line 54 - column 3, line 34; figures 3,5,6 *; | [X]EP0584910 (ADVANCED MICRO DEVICES INC [US]) [X] 1-7,15,16 * page 4, line 41 - page 5, line 49; figures 1,2 *; | [A]US5561773 (KALISH DAVID M [US], et al) [A] 1-16* column 1, line 12 - column 2, line 21; figure 2 *; | [X] - AGRAWAL O P, "AMD'S NEXT GENERATION MACHTM3XX/4XX FAMILY BREAKS NEW PLD DENSITY/SPEED BARRIER", WESCON TECHNICAL PAPERS, (19921117), vol. 36, pages 100 - 106, XP000350080 [X] 1-7,15,16 * page 102, paragraph 3 - page 102, paragraph 7; figure 3 * |