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EP0878769
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EP About this file: EP0878769
| EP0878769 - Method for verification of combinational circuits using a filtering oriented approach [Right-click to bookmark this link] | Status | The application is deemed to be withdrawn Status updated on 03.04.2009 Database last updated on 24.04.2024 | Most recent event Tooltip | 03.04.2009 | Application deemed to be withdrawn | published on 06.05.2009 [2009/19] | Applicant(s) | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi Kanagawa 211-8588 / JP | [N/P] |
| Former [1998/47] | For all designated states FUJITSU LIMITED 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 / JP | Inventor(s) | 01 /
Jain, Jawahar 3500 Granada Avenue 164, Santa Clara, California 95051 / US | 02 /
Mukherjee, Rajarshi 750 N.King Road 302, San Jose, California 95133 / US | 03 /
Takayama, Koichiro 52-5-507 Matsugaya, Hachioji Tokyo 192-03 / JP | [1998/47] | Representative(s) | Stebbing, Timothy Charles, et al Haseltine Lake LLP Lincoln House, 5th Floor 300 High Holborn London WC1V 7JH / GB | [N/P] |
| Former [1998/47] | Stebbing, Timothy Charles, et al Haseltine Lake & Co., Imperial House, 15-19 Kingsway London WC2B 6UD / GB | Application number, filing date | 98303748.2 | 13.05.1998 | [1998/47] | Priority number, date | US19970857916 | 16.05.1997 Original published format: US 857916 | [1998/47] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0878769 | Date: | 18.11.1998 | Language: | EN | [1998/47] | Type: | A3 Search report | No.: | EP0878769 | Date: | 21.06.2000 | [2000/25] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 04.05.2000 | Classification | IPC: | G06F17/50 | [1998/47] | CPC: |
G01R31/318357 (EP,US);
G01R31/318371 (EP,US);
G01R31/318385 (EP,US);
G06F30/3323 (EP,US)
| Designated contracting states | DE, FR [2001/09] |
| Former [1998/47] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Verfahren zur Verifikation kombinatorischer Schaltungen mit einem filter-basierenden Ansatz | [1998/47] | English: | Method for verification of combinational circuits using a filtering oriented approach | [1998/47] | French: | Procédé pour vérifier des circuits combinatoires utilisant des filtres | [1998/47] | Examination procedure | 27.09.2000 | Examination requested [2000/47] | 21.02.2002 | Despatch of a communication from the examining division (Time limit: M04) | 29.06.2002 | Reply to a communication from the examining division | 19.11.2002 | Despatch of a communication from the examining division (Time limit: M04) | 28.03.2003 | Reply to a communication from the examining division | 18.07.2003 | Despatch of a communication from the examining division (Time limit: M06) | 27.01.2004 | Reply to a communication from the examining division | 24.08.2004 | Despatch of a communication from the examining division (Time limit: M06) | 03.03.2005 | Reply to a communication from the examining division | 23.12.2005 | Despatch of a communication from the examining division (Time limit: M04) | 24.03.2006 | Reply to a communication from the examining division | 01.08.2006 | Despatch of a communication from the examining division (Time limit: M02) | 05.10.2006 | Reply to a communication from the examining division | 23.05.2007 | Despatch of a communication from the examining division (Time limit: M02) | 30.07.2007 | Reply to a communication from the examining division | 01.07.2008 | Communication of intention to grant the patent | 12.11.2008 | Application deemed to be withdrawn, date of legal effect [2009/19] | 16.12.2008 | Despatch of communication that the application is deemed to be withdrawn, reason: fee for grant / fee for printing not paid in time [2009/19] | Fees paid | Renewal fee | 24.05.2000 | Renewal fee patent year 03 | 23.05.2001 | Renewal fee patent year 04 | 27.05.2002 | Renewal fee patent year 05 | 27.05.2003 | Renewal fee patent year 06 | 26.05.2004 | Renewal fee patent year 07 | 27.05.2005 | Renewal fee patent year 08 | 31.03.2006 | Renewal fee patent year 09 | 31.05.2007 | Renewal fee patent year 10 | 17.03.2008 | Renewal fee patent year 11 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Documents cited: | Search | [A]EP0726538 (FUJITSU LTD [JP]) [A] 22* column 1, line 1 - column 6, line 35 *; | [XA] - BRYANT R E ET AL, "Verification of arithmetic circuits with Binary Moment Diagrams", 32ND DESIGN AUTOMATION CONFERENCE. PROCEEDINGS 1995 (IEEE CAT. NO.95CH35812), PROCEEDINGS OF 32ND DESIGN AUTOMATION CONFERENCE, SAN FRANCISCO, CA, USA, 12-16 JUNE 1995, 1995, New York, NY, USA, ACM, USA, ISBN 0-89791-725-1, pages 535 - 541, XP000546358 [X] 1,2,14,15 * page 538, column 2, line 45 - page 539, column 2, line 30 * [A] 23 | [XA] - CHEN Y -A ET AL, "ACV: an arithmetic circuit verifier", 1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN. DIGEST OF TECHNICAL PAPERS (CAT. NO.96CB35991), PROCEEDINGS OF INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, SAN JOSE, CA, USA, 10-14 NOV. 1996, 1996, Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, ISBN 0-8186-7597-7, pages 361 - 365, XP000738433 [X] 1,2,14,15 * page 362, column 1, line 1 - page 363, column 1, line 28 * [A] 23 | [XP] - MUKHERJEE R ET AL, "Efficient combinational verification using BDDs and a hash table", PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. CIRCUITS AND SYSTEMS IN THE INFORMATION AGE. ISCAS '97 (CAT. NO.97CH35987), PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. CIRCUITS AND SYSTEMS IN TH, 1997, New York, NY, USA, IEEE, USA, ISBN 0-7803-3583-X, pages 1025 - 1028 vol.2, XP002120997 [XP] 1,2,14,15,23-25 * the whole document * DOI: http://dx.doi.org/10.1109/ISCAS.1997.621909 | [A] - MATSUNAGA Y, "An efficient equivalence checker for combinational circuits", 33RD DESIGN AUTOMATION CONFERENCE. PROCEEDINGS 1996 (IEEE CAT.NO.96CH35932), PROCEEDINGS OF 33RD DESIGN AUTOMATION CONFERENCE, LAS VEGAS, NV, USA, 3-7 JUNE 1996, 1996, New York, NY, USA, ACM, USA, ISBN 0-89791-779-0, pages 629 - 634, XP002120999 [A] 3,4,22-25 * page 631, column 1, line 10 - page 633, column 2, line 15 * * page 629, column 2, line 21 - page 630, column 2, line 18 * | [A] - JAIN J ET AL, "Formal verification of combinational circuits", PROCEEDINGS. TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN (CAT. NO.97TB100095), PROCEEDINGS TENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, HYDERABAD, INDIA, 4-7 JAN. 1997, 1997, Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, ISBN 0-8186-7755-4, pages 218 - 225, XP002120998 [A] 3-13,16-21,23-25 * the whole document * | [A] - BERMAN C L ET AL, "Functional comparison of logic designs for VLSI circuits", 1989 IEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN. DIGEST OF TECHNICAL PAPERS (CAT. NO.89CH2805-0), SANTA CLARA, CA, USA, 5-9 NOV. 1989, 1989, Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, ISBN 0-8186-1986-4, pages 456 - 459, XP000164206 [A] 22 * the whole document * DOI: http://dx.doi.org/10.1109/ICCAD.1989.76990 | [A] - CHANG S -C ET AL, "Technology mapping via transformations of function graphs", IEEE 1992 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS. ICCD '92 (CAT. NO.92CH3189-8), CAMBRIDGE, MA, USA, 11-14 OCT. 1992, 1992, Los Alamitos, CA, USA, IEEE Comput. Soc. Press, USA, ISBN 0-8186-3110-4, pages 159 - 162, XP000344603 [A] 22 * page 159, column 2, line 17 - page 161, column 1, line L * |