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EP0979000
European procedure
Extract from the Register of European Patents
EP About this file: EP0979000
| EP0979000 - Phase lock loop with selectable response [Right-click to bookmark this link] | Status | No opposition filed within time limit Status updated on 12.10.2007 Database last updated on 03.10.2024 | Most recent event Tooltip | 15.08.2008 | Change - representative | published on 17.09.2008 [2008/38] | Applicant(s) | For all designated states THOMSON CONSUMER ELECTRONICS, INC. 10330 North Meridian St. Indianapolis, IN 46206 / US | [2000/06] | Inventor(s) | 01 /
Wilber, James Albert 931 N. Arlington Drive Indianapolis, IN 46219 / US | [2000/06] | Representative(s) | Arnold, Klaus-Peter Deutsche Thomson OHG Karl-Wiechert-Allee 1D 30625 Hannover / DE | [N/P] |
| Former [2008/38] | Arnold, Klaus-Peter Deutsche Thomson OHG European Patent Operations Karl-Wiechert-Allee 74 30625 Hannover / DE | ||
| Former [2005/19] | Arnold, Klaus-Peter, Dr. Deutsche Thomson-Brandt GmbH European Patent Operations Karl-Wiechert-Allee 74 30625 Hannover / DE | ||
| Former [2000/06] | Rossmanith, Manfred, Dr., et al Deutsche Thomson-Brandt GmbH, Licensing & Intellectual Property, Karl-Wiechert-Allee 74 30625 Hannover / DE | Application number, filing date | 99115011.1 | 30.07.1999 | [2000/06] | Priority number, date | US19980130977 | 07.08.1998 Original published format: US 130977 | [2000/06] | Filing language | EN | Procedural language | EN | Publication | Type: | A2 Application without search report | No.: | EP0979000 | Date: | 09.02.2000 | Language: | EN | [2000/06] | Type: | A3 Search report | No.: | EP0979000 | Date: | 28.01.2004 | [2004/05] | Type: | B1 Patent specification | No.: | EP0979000 | Date: | 06.12.2006 | Language: | EN | [2006/49] | Search report(s) | (Supplementary) European search report - dispatched on: | EP | 12.12.2003 | Classification | IPC: | H04N5/12 | [2000/06] | CPC: |
H04N5/126 (EP,US);
H04N5/12 (KR);
H03L7/093 (EP,US);
H04N5/46 (EP,US)
| Designated contracting states | DE, ES, FR, GB, IT [2004/43] |
| Former [2000/06] | AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LI, LU, MC, NL, PT, SE | Title | German: | Phasenregelkreis mit wählbarer Antwort | [2000/06] | English: | Phase lock loop with selectable response | [2000/06] | French: | Boucle à verrouillage de phase à réponse sélective | [2000/06] | Examination procedure | 02.07.2004 | Examination requested [2004/36] | 28.07.2004 | Despatch of a communication from the examining division (Time limit: M06) | 14.03.2005 | Despatch of communication that the application is deemed to be withdrawn, reason: reply to the communication from the examining division not received in time | 13.05.2005 | Reply to a communication from the examining division | 31.10.2005 | Despatch of a communication from the examining division (Time limit: M06) | 05.05.2006 | Reply to a communication from the examining division | 16.06.2006 | Communication of intention to grant the patent | 23.10.2006 | Fee for grant paid | 23.10.2006 | Fee for publishing/printing paid | Opposition(s) | 07.09.2007 | No opposition filed within time limit [2007/46] | Request for further processing for: | 13.05.2005 | Request for further processing filed | 13.05.2005 | Full payment received (date of receipt of payment) Request granted | 31.05.2005 | Decision despatched | Fees paid | Renewal fee | 11.07.2001 | Renewal fee patent year 03 | 28.06.2002 | Renewal fee patent year 04 | 16.07.2003 | Renewal fee patent year 05 | 20.07.2004 | Renewal fee patent year 06 | 21.07.2005 | Renewal fee patent year 07 | 21.07.2006 | Renewal fee patent year 08 |
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| Responsibility for the accuracy, completeness or quality of the data displayed under the link provided lies entirely with the Unified Patent Court. | Lapses during opposition Tooltip | IT | 06.12.2006 | ES | 17.03.2007 | [2008/16] | Documents cited: | Search | [Y]US4024464 (UNDERHILL MICHAEL JAMES, et al) [Y] 1-20* column 2, line 67 - column 3, line 54; figure 1 *; | [Y]US5495512 (KOVACS JANOS [US], et al) [Y] 1-20 * abstract * * column 4, line 2 - column 5, line 29; figure 1 *; | [Y] - CAMPBELL E R ET AL, "FULL CMOS VIDEO LINE-LOCKED PHASE-LOCKED LOOP SYSTEM", PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS. ROSEMONT, JUNE 8 - 10, 1993, NEW YORK, IEEE, US, (19930608), vol. CONF. 12, pages 256 - 257, XP000427607 [Y] 1-20 * column W * |